Power/performance/channel length tradeoffs in 1.6 to 9.6Gbps I/O links in 90nm CMOS for server, desktop, and mobile applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 79-80

  Yeung, Evelina ^a   Canagasaby, Karthisha ^a   Tripathi, Alok ^a   Chaudhuri, Santanu ^a   Meier, Pascal ^a   Prijic, James ^a   Joshi, Vivek ^a   Mazumder, Mohiuddin ^a   Dabral, Sanjay ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Equalizer; I O link; Low power; Voltage mode driver

Indexed keywords

CHANNEL CAPACITY; LOW POWER ELECTRONICS; SERVERS;

RX CLOCKING SCHEMES; RX EQUALIZERS; VOLTAGE MODE DRIVER;

CMOS INTEGRATED CIRCUITS;

EID: 39749143980     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A.X. Widmer, et al., "Single-Chip 4*500-MBd CMOS Transceiver," ISSCC, p. 126-127, Feb. 1996.
2. P. Landman, et al., "A TX Architecture with 4-Tap Feedforward Equalizer for 6.25/12.5Gb/s Serial Backplane Communications," ISSCC, p. 66-67, Feb. 2005.
3. E. Yeung, et al., "A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with Per Pin Skew Compensation," ISSCC, p. 256-257, Feb. 2000.
4. J. Zerbe, et al., "Equalization and Clock Recovery for a 2.5-10-Gb/s 2-PAM/4-PAM Backplane Transceiver Cell," ISSCC, p. 80-81, Feb. 2003.