12Gb/s duobinary signaling with ×2 oversampled edge equalization

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Yamaguchi, Kouichi ^a   Sunaga, Kazuhisa ^a   Kaeriyama, Shunichi ^a   Nedachi, Takaaki ^a   Takamiya, Makoto ^a   Nose, Kouichi ^a   Nakagawa, Yoshihiro ^a   Sugawara, Mitsutoshi ^a   Fukaishi, Muneo ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144439863     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. A. Lender, "The Duobinary Technique for High-Speed Data Transmission," IEEE Trans. Commun. Electron., vol. 82, pp. 214-218, May, 1963.
2. J. L. Zerbe et al., "Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell", IEEE J. Solid-State Circuits, vol. 38, pp. 2121-2130, Dec., 2003.