A low-power receiver with switched-capacitor summation DFE

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 192-193

  Emami Neyestanak, Azita ^a   Varzaghani, Aida ^b   Bulzacchelli, John ^a   Rylyakov, Alexander ^a   Yang, Chih Kong Ken ^b   Friedman, Daniel ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

DFE; High speed IO; Interconnect; Receiver

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; SWITCHING NETWORKS;

CLOCK BUFFERS; POWER RECEIVERS;

DECISION FEEDBACK EQUALIZERS;

EID: 34748905629     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. V. Stojanovic et al., "Adaptive Equalization and Data Recovery in a Dual-Mode (PAM2/4) Serial Link Transceiver," IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 348-351, June 2004
2. T. Beukema et al., "A 6.4-Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization," IEEE J. Solid-State Circuits, vol. 40, pp. 2633-45, Dec. 2005
3. R. Payne et al., "A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Solid-State Circuits, pp. 2646-57, Dec. 2005
4. G. M. Haller and B. A. Wooley, "A 700-MHz SwitchedCapacitor Analog Waveform Sampling Circuit," IEEE J. Solid-State Circuits, vol. 29, pp. 500-508, Apr. 1994
5. S.-J. Bae, H.-J. Chi, Y.-S. Sohn, and H.-J. Park, "A 2Gb/s 2-tap DFE Receiver for Multi-Drop Single-Ended Signaling Systems with Reduced Noise", ISSCC Dig. Tech. Papers, pp. 244-245, Feb 2004