Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 14-15

  Tomita, K ^a   Hashimoto, K ^a   Inbe, T ^a   Oashi, T ^a   Tsukamoto, K ^a   Nishioka, Y ^a   Matsuura, M ^a   Eimori, T ^a   Inuishi, M ^a   Miyanaga, I ^a   Nakamura, M ^a   Kishimoto, T ^a   Yamada, T ^a   Eriguchi, K ^a   Yuasa, H ^a   Satake, T ^a   Kajiya, A ^a   Ogura, M ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; LITHOGRAPHY; MASKS; PHASE SHIFT; SCANNING ELECTRON MICROSCOPY; TRANSISTORS; TRANSMISSION ELECTRON MICROSCOPY;

SHALLOW TRENCH ISOLATION (STI);

STATIC RANDOM ACCESS STORAGE;

EID: 0036051675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)