A 65nm low power CMOS platform with 0.495μm2 SRAM for digital processing and mobile applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 216-217

  Utsumi, K ^a   Morifuji, E ^a   Kanda, M ^a   Aota, S ^a   Yoshida, T ^a   Honda, K ^a   Matsubara, Y ^a   Yamada, S ^a   Matsuoka, F ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MOBILE TELECOMMUNICATION SYSTEMS; OPTIMIZATION; OXIDATION; STATIC RANDOM ACCESS STORAGE;

GATE OXIDATION PROCESS; HALO IMPLANTATION; HIGH DENSITY SRAM; PULSE NITRIDATION;

DIGITAL SIGNAL PROCESSING;

EID: 33745179186     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469273     Document Type: Conference Paper

References (4)

1. M.Kanda, et al., Symp. on VLSI Technology 2003 p.13.
2. Z. Luo, et al., IEDM 2004, p.661.
3. A.Chatterjee, el al., IKDM 2004. p.665.
4. E.Morifuji, et al., Symp. on VLSI Technology 2004 p. 164.