Highly Stable 65 nm Node (CMOS5) 0.56μm2 SRAM Cell Design for Very Low Operation Voltage

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 13-14

  Kanda, M ^a   Morifuji, E ^a   Nishigoori, M ^a   Fujimoto, Y ^a   Uematsu, M ^b   Takahashi, K ^a   Tsuno, H ^a   Okano, K ^a   Matsuda, S ^a   Oyamatsu, H ^a   Takahashi, H ^b   Nagashima, N ^b   Yamada, S ^a   Noguchi, T ^a   Okamoto, Y ^b   Kakumu, M ^a  

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; GATES (TRANSISTOR); LEAKAGE CURRENTS; LITHOGRAPHY; SCANNING ELECTRON MICROSCOPY; SPURIOUS SIGNAL NOISE; STATIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT DESIGN;

STATIC NOISE MARGIN (SNM);

CMOS INTEGRATED CIRCUITS; SYSTEM-ON-CHIP;

65-NM-NODE; 6T-SRAM; 6T-SRAMS; CELL DESIGN; HIGHLY STABLES; OPERATION VOLTAGE; PERFORMANCE; SOC PLATFORMS; SRAM CELL;

EID: 0141426850     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Soon-Moon.Jung et al., IEDM Tech. Dig., p.419, 2002
2. Y.Fukaura et al., IEDM Tech. Dig., p.415, 2002
3. N.Yanagiya et al., IEDM Tech. Dig., p.57, 2002