Design criteria of high-voltage lateral RESURF JFETs on 4H-SiC

IEEE Transactions on Electron Devices

Volumn 52, Issue 10, 2005, Pages 2300-2308

  Sheng, Kuang ^a,b   Hu, Shuntao ^b  

^a IEEE   (United States)

^b RUTGERS UNIVERSITY   (United States)

Author keywords

Junction field effect transistor (JFET); Power integrated circuits; Power semiconductor switches; Reduced surface electric field (RESURF) effect; SiC; Voltage

Indexed keywords

JUNCTION FIELD-EFFECT TRANSISTOR (JFET); POWER SEMICONDUCTOR SWITCHES; REDUCED SURFACE ELECTRIC FIELD (RESURF) EFFECT;

ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE; FIELD EFFECT TRANSISTORS; LOGIC DESIGN; OPTIMIZATION; POWER INTEGRATED CIRCUITS; SILICON CARBIDE;

POWER ELECTRONICS;

EID: 33947422568     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.856177     Document Type: Article

References (18)

1. K. Tone, J. H. Zhao, L. Fursin, P. Alexandrov, and M. Weiner, "4 H-SiC normally off vertical junction field-effect transistor with high current density," IEEE Electron Device Lett., vol. 24, no. 7, pp. 463-465, Jul. 2003.
2. S. Sridevan and J. Baliga, "Lateral n-channel inversion mode 4H-SiC MOSFETs," IEEE Electron Device Lett., vol. 19, no. 7, pp. 228-230, Jul. 1998.
3. J. Spitz, M. R. Melloch, J. A. Cooper, Jr., and M. A. Capano, "2.6 kV 4H-SiC lateral DMOSFETs," IEEE Electron Device Lett., vol. 19, no. 4, pp. 100-102, Apr. 1998.
4. K. Chatty, S. Banerjee, T. P. Chow, R. J. Gutmann, and M. Hoshi, "High-voltage lateral RESURF MOSFETs on 4H-SiC," in Proc. Device Research Conf., 1999, pp. 44-45.
5. K. Chatty, S. Banerjee, T. P. Chow, and R. J. Gutmann, "High-voltage lateral RESURF MOSFETs on 4H-SiC," IEEE Electron Device Lett., vol. 21, no. 7, pp. 356-358, Jul. 2000.
6. S. Banerjee, K. Chatty, T. P. Chow, and R. J. Gutmann, "Improved implanted RESURF MOSFETs in 4H-SiC," in Proc. Device Research Conf., 2000, pp. 129-130.
7. _, "Improved high-voltage lateral RESURF MOSFETs in 4H-SiC," IEEE Electron Device Lett., vol. 22, no. 5, pp. 209-211, May 2001.
8. 2, lateral, two-zone RESURF MOSFETs in 6H-SiC," in Proc. Int. Power Semiconductor Devices and ICs Symp., 2002, pp. 69-72.
9. _, "1300-V 6H-SiC lateral MOSFETs with two RESURF zones," IEEE Electron Device Lett., vol. 23, no. 10, pp. 624-626, Oct. 2002.
10. 2 lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealina," IEEE Electron Device Lett., vol. 25, no. 4, pp. 185-187, Apr. 2004.
11. M. Ruff, H. Mitlehner, and R. Helbig, "SiC devices: Physics and numerical simulation," IEEE Trans. Electron Devices, vol. 41, no. 6, pp. 1040-1054, Jun. 1994.
12. M. Bakowski, U. Gustafsson, and U. Lindefelt, "Simulation of SiC high power devices," Phys. Stat. Sol. (A), vol. 162, pp. 421-440, 1997.
13. A. W. Ludikhuize, "A review of RESURF technology," in Proc. Int. Power Semiconductor Devices and ICs Symp., 2000, pp. 11-18.
14. M. Imam, Z. Hossain, M. Quddus, J. Adams, C. Hoggatt, T. Ishiguro, and R. Nair, "Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process," IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1697-1700, Jul. 2003.
15. M. Roschke and F. Schwierz, "Electron mobility models for 4H, 6H, and 3C SiC," IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 1442-1447, Nov. 2001.
16. R. Ng, F. Udrea, K. Sheng, K. Ueno, G. A. J. Amaratunga, and M. Nishiura, "Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI," in IEEE Int. Symp. Power Semiconductor Devices and ICs (ISPSD), Osaka, Japan, 2001, pp. 395-398.
17. S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, "Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors," in Proc. ISPSD, May 18-20, 1993, pp. 124-128.
18. K. Fujikawa, K. Shibata, T. Masuda, S. Shikata, and H. Hayashi, "800 V 4H-SiC RESURF-Type Lateral JFETs," IEEE Electron Device Lett., vol. 25, no. 12, pp. 790-791, Dec. 2004.