-
1
-
-
13844275618
-
"In search of 'forever,' continued transistor scaling one new material at a time"
-
Feb
-
S. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, and M. T. Bohr, "In search of 'forever,' continued transistor scaling one new material at a time," IEEE Trans. Semicond. Manuf., vol. 18, no. 1, pp. 26-36, Feb. 2005.
-
(2005)
IEEE Trans. Semicond. Manuf.
, vol.18
, Issue.1
, pp. 26-36
-
-
Thompson, S.1
Chau, R.S.2
Ghani, T.3
Mistry, K.4
Tyagi, S.5
Bohr, M.T.6
-
2
-
-
18644382452
-
"Hole mobility enhancements and alloy scattering-limited mobility in tensile strained-Si/SiGe surface channel metal-oxide-semiconductor field-effect transistors"
-
Oct
-
C. W. Leitz, M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis, and E. A. Fitzgerald, "Hole mobility enhancements and alloy scattering-limited mobility in tensile strained-Si/SiGe surface channel metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 92, no. 7, pp. 3745-3751, Oct. 2002.
-
(2002)
J. Appl. Phys.
, vol.92
, Issue.7
, pp. 3745-3751
-
-
Leitz, C.W.1
Currie, M.T.2
Lee, M.L.3
Cheng, Z.-Y.4
Antoniadis, D.A.5
Fitzgerald, E.A.6
-
3
-
-
0043269756
-
"Six-band k - P calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness"
-
Jul
-
M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, "Six-band k - p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness," J. Appl. Phys., vol. 94, no. 2, pp. 1079-1095, Jul. 2003.
-
(2003)
J. Appl. Phys.
, vol.94
, Issue.2
, pp. 1079-1095
-
-
Fischetti, M.V.1
Ren, Z.2
Solomon, P.M.3
Yang, M.4
Rim, K.5
-
4
-
-
0036927652
-
"Strained silicon MOSFET technology"
-
J. L. Hoyt, H. M. Nayfeh, S. Equchi, I. Aberq, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, "Strained silicon MOSFET technology," in IEDM Tech. Dig., 2002, pp. 23-26.
-
(2002)
IEDM Tech. Dig.
, pp. 23-26
-
-
Hoyt, J.L.1
Nayfeh, H.M.2
Equchi, S.3
Aberq, I.4
Xia, G.5
Drake, T.6
Fitzgerald, E.A.7
Antoniadis, D.A.8
-
5
-
-
4544320963
-
"Understanding stress enhanced performance in Intel 90 nm CMOS technology"
-
in ses. 12.2
-
M. D. Giles, M. Armstrong, C. Auth, S. M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weher, and K. Zawadzki, "Understanding stress enhanced performance in Intel 90 nm CMOS technology," in VLSI Symp. Tech. Dig., 2004, pp. 118-119, ses. 12.2.
-
(2004)
VLSI Symp. Tech. Dig.
, pp. 118-119
-
-
Giles, M.D.1
Armstrong, M.2
Auth, C.3
Cea, S.M.4
Ghani, T.5
Hoffmann, T.6
Kotlyar, R.7
Matagne, P.8
Mistry, K.9
Nagisetty, R.10
Obradovic, B.11
Shaheed, R.12
Shifren, L.13
Stettler, M.14
Tyagi, S.15
Wang, X.16
Weher, C.17
Zawadzki, K.18
-
6
-
-
20544447617
-
"Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs"
-
S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig., 2004, pp. 221-224.
-
(2004)
IEDM Tech. Dig.
, pp. 221-224
-
-
Thompson, S.E.1
Sun, G.2
Wu, K.3
Lim, J.4
Nishida, T.5
-
7
-
-
11144354892
-
"A logic nanotechnology featuring strained-silicon"
-
Apr
-
S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.4
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Ma, Z.9
Mcintyre, B.10
Murthy, A.11
Obradovic, B.12
Shifren, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
-
8
-
-
3242671509
-
"A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors"
-
T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig., 2003, pp. 11.6.1-11.6.3.
-
(2003)
IEDM Tech. Dig.
-
-
Ghani, T.1
Armstrong, M.2
Auth, C.3
Bost, M.4
Charvat, P.5
Glass, G.6
Hoffmann, T.7
Johnson, K.8
Kenyon, C.9
Klaus, J.10
McIntyre, B.11
Mistry, K.12
Murthy, A.13
Sandford, J.14
Silberstein, M.15
Sivakumar, S.16
Smith, P.17
Zawadzki, K.18
Thompson, S.19
Bohr, M.20
more..
-
9
-
-
4544284412
-
"35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS"
-
in ses. 6.1
-
P. R. Chidambaram, "35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS," in VLSI Symp. Tech. Dig., 2004, pp. 48-49. ses. 6.1.
-
(2004)
VLSI Symp. Tech. Dig.
, pp. 48-49
-
-
Chidambaram, P.R.1
-
10
-
-
5444249918
-
"Stress management in sub-90-nm transistor architecture"
-
Oct
-
R. Arghavani, Z. Yuan, N. Ingle, K.-B. Jung, M. Seamons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, and A. Mascarenhas, "Stress management in sub-90-nm transistor architecture," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1740-1743, Oct. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.10
, pp. 1740-1743
-
-
Arghavani, R.1
Yuan, Z.2
Ingle, N.3
Jung, K.-B.4
Seamons, M.5
Venkataraman, S.6
Banthia, V.7
Lilja, K.8
Leon, P.9
Karunasiri, G.10
Yoon, S.11
Mascarenhas, A.12
-
11
-
-
78649307395
-
"Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixture"
-
Oct
-
R. E. Beaty, R. C. Jaeger, J. C. Suhling, R. W. Johnson, and R. D. Butler, "Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixture," IEEE Trans. Compon., Hybrids, Manuf. Technol., vol. 15, no. 5, pp. 904-914, Oct. 1992.
-
(1992)
IEEE Trans. Compon., Hybrids, Manuf. Technol.
, vol.15
, Issue.5
, pp. 904-914
-
-
Beaty, R.E.1
Jaeger, R.C.2
Suhling, J.C.3
Johnson, R.W.4
Butler, R.D.5
-
12
-
-
33846693940
-
"Piezoresistance effect in germanium and silicon"
-
Apr
-
C. S. Smith, "Piezoresistance effect in germanium and silicon," Phys. Rev., vol. 94, no. 1, pp. 42-49, Apr. 1954.
-
(1954)
Phys. Rev.
, vol.94
, Issue.1
, pp. 42-49
-
-
Smith, C.S.1
-
13
-
-
20444482091
-
"Drive current enhancement in p-type metal-oxide-semiconductor field-effect transistors under shear uniaxial stress"
-
L. Shifren, X. Wang, P. Matagne, B. Obradovic, C. Auth, S. Cea, T. Ghani, J. He, T. Hoffman, R. Kotlyar, Z. Ma, K. Mistry, R. Nagisetty, R. Shaheed, M. Stettler, C. Weber, and M. D. Giles, "Drive current enhancement in p-type metal-oxide-semiconductor field-effect transistors under shear uniaxial stress," Appl. Phys. Lett., vol. 85, no. 2, p. 6188, 2004.
-
(2004)
Appl. Phys. Lett.
, vol.85
, Issue.2
, pp. 6188
-
-
Shifren, L.1
Wang, X.2
Matagne, P.3
Obradovic, B.4
Auth, C.5
Cea, S.6
Ghani, T.7
He, J.8
Hoffman, T.9
Kotlyar, R.10
Ma, Z.11
Mistry, K.12
Nagisetty, R.13
Shaheed, R.14
Stettler, M.15
Weber, C.16
Giles, M.D.17
-
14
-
-
21644476193
-
"Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress"
-
E. Wang, P. Matagne, L. Shifren, B. Obradovic, R. Kotlyar, S. Cea, J. He, Z. Ma, R. Nagisetty, S. Tyagi, M. Stettler, and M. D. Giles, "Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress," in IEDM Tech. Dig., 2004, pp. 147-150.
-
(2004)
IEDM Tech. Dig.
, pp. 147-150
-
-
Wang, E.1
Matagne, P.2
Shifren, L.3
Obradovic, B.4
Kotlyar, R.5
Cea, S.6
He, J.7
Ma, Z.8
Nagisetty, R.9
Tyagi, S.10
Stettler, M.11
Giles, M.D.12
-
15
-
-
0031191310
-
"Elementary scattering theory of the Si MOSFET"
-
Jul
-
M. Lundstrom, "Elementary scattering theory of the Si MOSFET," IEEE Electron Device Lett., vol. 18, no. 7, pp. 361-363, Jul. 1997.
-
(1997)
IEEE Electron Device Lett.
, vol.18
, Issue.7
, pp. 361-363
-
-
Lundstrom, M.1
-
16
-
-
31544445524
-
"A reliable and manufacturable method to induce a stress of > 1 GPa on a p-channel MOSFET in high volume manufacturing"
-
Feb
-
R. Arghavani, L. Xia, H. M'Saad, M. Balseanu, G. Karunasiri, A. Mascarenhas, and S. E. Thompson, "A reliable and manufacturable method to induce a stress of > 1 GPa on a p-channel MOSFET in high volume manufacturing," IEEE Electron Device Lett., vol. 27, no. 2, pp. 114-116, Feb. 2006.
-
(2006)
IEEE Electron Device Lett.
, vol.27
, Issue.2
, pp. 114-116
-
-
Arghavani, R.1
Xia, L.2
M'Saad, H.3
Balseanu, M.4
Karunasiri, G.5
Mascarenhas, A.6
Thompson, S.E.7
-
17
-
-
2942672642
-
"MC simulation of strained-Si MOSFET with full-band structure and quantum correction"
-
Jun
-
X.-F. Fan, X. Wang, B. Winstead, L. F. Register, U. Ravaioli, and S. K. Banerjee, "MC simulation of strained-Si MOSFET with full-band structure and quantum correction," IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 962-970, Jun. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.6
, pp. 962-970
-
-
Fan, X.-F.1
Wang, X.2
Winstead, B.3
Register, L.F.4
Ravaioli, U.5
Banerjee, S.K.6
-
18
-
-
33847662214
-
3 - A state-of-the-art simulation tool for 3 D quantum nanodevices"
-
in Munich, Germany: Walter Schottky Inst., TU Munich
-
3 - A state-of-the-art simulation tool for 3 D quantum nanodevices," in Annual Report 2001. Munich, Germany: Walter Schottky Inst., TU Munich, 2002.
-
(2002)
Annual Report 2001
-
-
Birner, S.1
Hackenbuchner, S.2
Majewski, J.A.3
Mamaluy, D.4
Sabathil, M.5
Zandler, G.6
-
19
-
-
0000693504
-
"Hole drift velocity in silicon"
-
Oct
-
G. Ottaviani, L. Reggiani, C. Canali, F. Nava, and A. Alberigi-Quaranta, "Hole drift velocity in silicon," Phys. Rev. B, Condens. Matter, vol. 12, no. 8, p. 3318, Oct. 1975.
-
(1975)
Phys. Rev. B, Condens. Matter
, vol.12
, Issue.8
, pp. 3318
-
-
Ottaviani, G.1
Reggiani, L.2
Canali, C.3
Nava, F.4
Alberigi-Quaranta, A.5
-
20
-
-
2942650352
-
"Monte Carlo simulation of charge transport in Si-based heterostructure transistors"
-
Ph.D. dissertation, Univ. Texas at Austin, Austin, TX
-
X. Wang, "Monte Carlo simulation of charge transport in Si-based heterostructure transistors," Ph.D. dissertation, Univ. Texas at Austin, Austin, TX, 2002.
-
(2002)
-
-
Wang, X.1
-
21
-
-
0017453673
-
"Review of some charge transport properties of silicon"
-
Feb
-
C. Jacoboni, C. Canali, G. Ottaviani, and A. Alberigi-Quaranta, "Review of some charge transport properties of silicon," Solid State Electron., vol. 20, no. 2, p. 77, Feb. 1977.
-
(1977)
Solid State Electron.
, vol.20
, Issue.2
, pp. 77
-
-
Jacoboni, C.1
Canali, C.2
Ottaviani, G.3
Alberigi-Quaranta, A.4
-
22
-
-
33847697736
-
"Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime"
-
in 6.1
-
K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, "Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime," in IEDM Tech. Dig., 2005, pp. 129-132. 6.1.
-
(2005)
IEDM Tech. Dig.
, pp. 129-132
-
-
Uchida, K.1
Krishnamohan, T.2
Saraswat, K.C.3
Nishi, Y.4
|