Six subthreshold full adder cells characterized in 90 nm CMOS technology

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

Volumn 2006, Issue , 2006, Pages 25-30

  Granhaug, Kristian ^a   Aunet, Snorre ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION; NATURAL FREQUENCIES; TOPOLOGY;

ENERGY-DELAY PRODUCT (EDP); FULL ADDERS; POWER-DELAY PRODUCT (PDP);

ADDERS;

EID: 33847157236     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2006.1649565     Document Type: Conference Paper

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