-
1
-
-
0035054933
-
Microprocessors for the new millennium; Challenges, Opportunities, and New Frontiers
-
P. P. Gelsinger, "Microprocessors for the new millennium; Challenges, Opportunities, and New Frontiers," Digest of technical papers, 2001 IEEE Solid-State Circuits Conference, pp. 22-25, 2001.
-
(2001)
Digest of technical papers, 2001 IEEE Solid-State Circuits Conference
, pp. 22-25
-
-
Gelsinger, P.P.1
-
3
-
-
0035242870
-
Robust Subthreshold Logic for Ultra-Low Power Operation
-
Feb
-
H. Soeleman, K. Roy and B. C. Paul, "Robust Subthreshold Logic for Ultra-Low Power Operation," IEEE Transactions on Very large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 90-99, Feb. 2001.
-
(2001)
IEEE Transactions on Very large Scale Integration (VLSI) Systems
, vol.9
, Issue.1
, pp. 90-99
-
-
Soeleman, H.1
Roy, K.2
Paul, B.C.3
-
4
-
-
0036858382
-
A 175 mV Multiply Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture
-
Nov
-
J. T. Kao, M. Miyazaki and A. R. Chandrakasan, "A 175 mV Multiply Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1545-1554, Nov. 2002.
-
(2002)
IEEE Journal of Solid-State Circuits
, vol.37
, pp. 1545-1554
-
-
Kao, J.T.1
Miyazaki, M.2
Chandrakasan, A.R.3
-
5
-
-
84954088099
-
An intelligent MOS transistor featuring gatelevel weighted sum and threshold operations
-
Washington DC, USA, pp, Dec
-
T. Shibata and T. Ohmi, "An intelligent MOS transistor featuring gatelevel weighted sum and threshold operations," Technical Digest of International Electron Devices Meeting, Washington DC, USA, pp. 919-922, Dec. 1991.
-
(1991)
Technical Digest of International Electron Devices Meeting
, pp. 919-922
-
-
Shibata, T.1
Ohmi, T.2
-
7
-
-
3042510837
-
-
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
-
X. Xi, M. Dunga, J. He, W. Liu, K. M. Cao, X. Jin, J. J. Ou, M. Chan, A. M. Niknejad and C. Hu, "BSIM4.3.0 MOSFET Model - User's Manual," Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 2003.
-
(2003)
BSIM4.3.0 MOSFET Model - User's Manual
-
-
Xi, X.1
Dunga, M.2
He, J.3
Liu, W.4
Cao, K.M.5
Jin, X.6
Ou, J.J.7
Chan, M.8
Niknejad, A.M.9
Hu, C.10
-
8
-
-
14244249218
-
Body-Bias Compensation Technique for SubThreshold CMOS Static Logic Gates
-
Sep
-
L. A. P. Melek, M. C. Schneider and C. Galup-Montoro, "Body-Bias Compensation Technique for SubThreshold CMOS Static Logic Gates," SBCCI'04, Sep. 2004.
-
(2004)
SBCCI'04
-
-
Melek, L.A.P.1
Schneider, M.C.2
Galup-Montoro, C.3
-
9
-
-
0034860181
-
Low-Power CMOS at Vdd=4kT/q
-
A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan and E. J. Nowak, "Low-Power CMOS at Vdd=4kT/q," Dev. Res. Conf, 2001.
-
(2001)
Dev. Res. Conf
-
-
Bryant, A.1
Brown, J.2
Cottrell, P.3
Ketchen, M.4
Ellis-Monaghan, J.5
Nowak, E.J.6
-
10
-
-
42549099702
-
Three sub-fJ Power-Delay-Product Subthreshold CMOS Gates
-
Oct
-
S. Aunet and Y. Berg, "Three sub-fJ Power-Delay-Product Subthreshold CMOS Gates," IFlP VISI-SoC, Oct. 2005.
-
(2005)
IFlP VISI-SoC
-
-
Aunet, S.1
Berg, Y.2
-
11
-
-
10844292586
-
Reconfigurable Subthreshold CMOS Perceptron
-
Jun
-
S. Aunet, B. Oelmann, S. Abdalla and Y. Berg, "Reconfigurable Subthreshold CMOS Perceptron," International Joint Conference on Neural Networks (IJCNN), pp. 1983-1988, Jun. 2004.
-
(2004)
International Joint Conference on Neural Networks (IJCNN)
, pp. 1983-1988
-
-
Aunet, S.1
Oelmann, B.2
Abdalla, S.3
Berg, Y.4
-
12
-
-
0031674834
-
Single Electron Majority Logic Circuits
-
H. Iwamura, M. Akazawa and Y. Amemiya, "Single Electron Majority Logic Circuits," IEICE Transactions on Electronics, V E18 C, pp. 42-48, 1998.
-
(1998)
IEICE Transactions on Electronics
, vol.E18
, Issue.C
, pp. 42-48
-
-
Iwamura, H.1
Akazawa, M.2
Amemiya, Y.3
-
14
-
-
33847152434
-
Kretselement, Norwegian patent application
-
20035537 Trondheim, Dec
-
S. Aunet, "Kretselement, Norwegian patent application, no. 20035537," Leiv Eiriksson Nyskapning, Trondheim, Dec. 2003.
-
(2003)
Leiv Eiriksson Nyskapning
-
-
Aunet, S.1
-
15
-
-
0036507826
-
Maintaining the benefits of CMOS scaling when scaling bogs down
-
Mar./May
-
E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down." IBM J. Res. & Dev., vol. 46, no. 2/3. pp. 169-180, Mar./May 2002.
-
(2002)
IBM J. Res. & Dev
, vol.46
, Issue.2-3
, pp. 169-180
-
-
Nowak, E.J.1
-
17
-
-
84956966208
-
Real Time reconfigurable Threshold Elements and Some Applications to Neural Hardware, Pmceedings to International Conferance of Evolvable Systems: From Biology to Hardware
-
Mar. 17-20
-
S. Aunet and M. Hartmann, "Real Time reconfigurable Threshold Elements and Some Applications to Neural Hardware," Pmceedings to International Conferance of Evolvable Systems: From Biology to Hardware, LNCS 2606, pp. 365-376, Mar. 17-20, 2003.
-
(2003)
LNCS
, vol.2606
, pp. 365-376
-
-
Aunet, S.1
Hartmann, M.2
-
18
-
-
20344374324
-
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
-
Aug
-
A. Schmid and Y. Leblebici, "Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors," IEEE Conference on Nanotechnology, pp. 516-519, Aug. 2003.
-
(2003)
IEEE Conference on Nanotechnology
, pp. 516-519
-
-
Schmid, A.1
Leblebici, Y.2
-
19
-
-
0026124101
-
Current-Mode Subthreshold MOS Circuits for Analog VLSI Neural Systems
-
Mar
-
A. G. Andreou, K. A. Boahen, P. O. Pouliquen, A. Pavasović, R. E. Jenkins and K. Strohbehn, "Current-Mode Subthreshold MOS Circuits for Analog VLSI Neural Systems," IEEE Transactions on Neural Networks, vol. 2, no. 2, pp. 205-213, Mar. 1991.
-
(1991)
IEEE Transactions on Neural Networks
, vol.2
, Issue.2
, pp. 205-213
-
-
Andreou, A.G.1
Boahen, K.A.2
Pouliquen, P.O.3
Pavasović, A.4
Jenkins, R.E.5
Strohbehn, K.6
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