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Volumn , Issue , 2006, Pages 1255-1258

Body-bias regulator for ultra low power multifunction CMOS gates

Author keywords

[No Author keywords available]

Indexed keywords

BIAS CURRENTS; COMPUTER SIMULATION; ELECTRIC CURRENT REGULATORS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); HIGH TEMPERATURE EFFECTS; MONTE CARLO METHODS; PARAMETER ESTIMATION;

EID: 34547332059     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (19)
  • 4
    • 0036858382 scopus 로고    scopus 로고
    • A 175 mV Multiply Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture
    • Nov
    • J. T. Kao, M. Miyazaki and A. R. Chandrakasan, "A 175 mV Multiply Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1545-1554, Nov. 2002.
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , pp. 1545-1554
    • Kao, J.T.1    Miyazaki, M.2    Chandrakasan, A.R.3
  • 5
    • 84954088099 scopus 로고
    • An intelligent MOS transistor featuring gatelevel weighted sum and threshold operations
    • Washington DC, USA, pp, Dec
    • T. Shibata and T. Ohmi, "An intelligent MOS transistor featuring gatelevel weighted sum and threshold operations," Technical Digest of International Electron Devices Meeting, Washington DC, USA, pp. 919-922, Dec. 1991.
    • (1991) Technical Digest of International Electron Devices Meeting , pp. 919-922
    • Shibata, T.1    Ohmi, T.2
  • 8
    • 14244249218 scopus 로고    scopus 로고
    • Body-Bias Compensation Technique for SubThreshold CMOS Static Logic Gates
    • Sep
    • L. A. P. Melek, M. C. Schneider and C. Galup-Montoro, "Body-Bias Compensation Technique for SubThreshold CMOS Static Logic Gates," SBCCI'04, Sep. 2004.
    • (2004) SBCCI'04
    • Melek, L.A.P.1    Schneider, M.C.2    Galup-Montoro, C.3
  • 10
    • 42549099702 scopus 로고    scopus 로고
    • Three sub-fJ Power-Delay-Product Subthreshold CMOS Gates
    • Oct
    • S. Aunet and Y. Berg, "Three sub-fJ Power-Delay-Product Subthreshold CMOS Gates," IFlP VISI-SoC, Oct. 2005.
    • (2005) IFlP VISI-SoC
    • Aunet, S.1    Berg, Y.2
  • 14
    • 33847152434 scopus 로고    scopus 로고
    • Kretselement, Norwegian patent application
    • 20035537 Trondheim, Dec
    • S. Aunet, "Kretselement, Norwegian patent application, no. 20035537," Leiv Eiriksson Nyskapning, Trondheim, Dec. 2003.
    • (2003) Leiv Eiriksson Nyskapning
    • Aunet, S.1
  • 15
    • 0036507826 scopus 로고    scopus 로고
    • Maintaining the benefits of CMOS scaling when scaling bogs down
    • Mar./May
    • E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down." IBM J. Res. & Dev., vol. 46, no. 2/3. pp. 169-180, Mar./May 2002.
    • (2002) IBM J. Res. & Dev , vol.46 , Issue.2-3 , pp. 169-180
    • Nowak, E.J.1
  • 17
    • 84956966208 scopus 로고    scopus 로고
    • Real Time reconfigurable Threshold Elements and Some Applications to Neural Hardware, Pmceedings to International Conferance of Evolvable Systems: From Biology to Hardware
    • Mar. 17-20
    • S. Aunet and M. Hartmann, "Real Time reconfigurable Threshold Elements and Some Applications to Neural Hardware," Pmceedings to International Conferance of Evolvable Systems: From Biology to Hardware, LNCS 2606, pp. 365-376, Mar. 17-20, 2003.
    • (2003) LNCS , vol.2606 , pp. 365-376
    • Aunet, S.1    Hartmann, M.2
  • 18
    • 20344374324 scopus 로고    scopus 로고
    • Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
    • Aug
    • A. Schmid and Y. Leblebici, "Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors," IEEE Conference on Nanotechnology, pp. 516-519, Aug. 2003.
    • (2003) IEEE Conference on Nanotechnology , pp. 516-519
    • Schmid, A.1    Leblebici, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.