Current challenges in Ge MOS technology

ECS Transactions

Volumn 3, Issue 2, 2006, Pages 371-384

  Dimoulas, A ^a,d   Houssa, M ^b   Ritenour, A ^c   Fompeyrine, J ^d   Tsai, W ^e   Seo, J W ^f   Panayiotatos, Y ^a   Tsipas, P ^a   Brunco, D P ^b,g   Caymax, M ^b   Locquet, J P ^d   Dieker, Ch ^f  

^a INSTITUTE OF NANOSCIENCE AND NANOTECHNOLOGY   (Greece)

^b IMEC   (Belgium)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d IBM RESEARCH ZURICH   (Switzerland)

^e INTEL CORPORATION   (United States)

^f EPFL   (Switzerland)

^g Intel Corporation Belgium   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; ELECTRIC PROPERTIES; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION; PASSIVATION; SEMICONDUCTING GERMANIUM; SUBSTRATES;

GATE DIELECTRICS; HIGH MOBILITY METAL OXIDE FIELD EFFECT TRANSISTORS; JUNCTION LEAKAGE; MOS TECHNOLOGY;

MOS DEVICES;

EID: 33846951865     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2356297     Document Type: Conference Paper

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