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Volumn 2006, Issue , 2006, Pages 155-166

Balanced cache: Reducing conflict misses of direct-mapped caches through programmable decoders

Author keywords

[No Author keywords available]

Indexed keywords

BALANCED CACHE; CACHE SETS; CLOCK FREQUENCY; PROGRAMMABLE DECODERS;

EID: 33845906041     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2006.12     Document Type: Conference Paper
Times cited : (24)

References (30)
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  • 4
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    • LRU-based column associative caches
    • May
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    • Chung, B.1    Pmf, J.2
  • 10
    • 0033358971 scopus 로고    scopus 로고
    • Reducing power in superscalar processor caches using subbanking, multiple line buffers, and bit-line segmentation
    • K Ghose and MB Kamble, "Reducing power in superscalar processor caches using subbanking, multiple line buffers, and bit-line segmentation." In Proc. of IEEE Int. Symp. on Low Power Electronics and Design, 1999.
    • (1999) Proc. of IEEE Int. Symp. on Low Power Electronics and Design
    • Ghose, K.1    Kamble, M.B.2
  • 11
    • 0043136471 scopus 로고    scopus 로고
    • Improved indexing for cache miss reduction in embedded systems
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    • (2003) Proc. of Design Automation Conference
    • Givargis, T.1
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  • 14
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    • May
    • N. P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," In Proc. of IEEE Int. Symp. on Computer Architecture, pp. 364-373, May 1990.
    • (1990) Proc. of IEEE Int. Symp. on Computer Architecture , pp. 364-373
    • Jouppi, N.P.1
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    • A low-cost, 300-MHz, RISC CPU with attached media processor
    • Santhanam, S., et al. A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE Journal of Solid-State Circuits Vol. 33, NO. 11, 1998. pp. 1829-1839.
    • (1998) IEEE Journal of Solid-state Circuits Vol. 33 , Issue.11 , pp. 1829-1839
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  • 25
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    • A divided word-line structure in the static RAM and its application to a 64k full CMOS RAM
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    • Balanced instruction cache: Reducing conflict misses of direct-mapped caches through balanced subarray accesses
    • May
    • C. Zhang, "Balanced Instruction Cache: Reducing Conflict Misses of Direct-Mapped Caches through Balanced Subarray Accesses," IEEE Computer Architecture Letter, May 2005.
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  • 30
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    • Sep/Oct
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.