On-die clock jitter detector for high speed microprocessors

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 187-190

  Kuppuswamy, R ^a   Callahan, K ^a   Wong, K ^a   Ratchen, D ^a   Taylor, G ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FILTERING; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; JITTER; PHASE LOCKED LOOPS; POWER SUPPLY CIRCUITS;

CLOCK JITTERS;

MICROPROCESSOR CHIPS;

EID: 0034795378     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 450 MHz IA32 P6 family microprocessor
2. A 0.35μm CMOS 2-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors
3. A delay line loop for frequency synthesis of deskewed clock
4. Low-jitter process-independent DLL and PLL based on self-biased techniques