A sub-10ps multi-phase sampling system using redundancy

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Lee, Li Min ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144442739     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Editorial

References (4)

1. D. Weinlader et al., "An Eight Channel 36GSample/s CMOS Timing Analyzer," ISSCC Dig. Tech. Papers, pp. 170-171, Feb., 2000.
2. K.L.J. Wong et al, "A 27-mW 3.6-Gb/s I/O Transceiver," Symp. VLSI Circuits, pp. 99-102, Jun., 2003.
3. J. Maneatis, "Low-Jitter Process-Independent DLL and PLL based on Self-Biased Techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov., 1996.
4. T. Knotts et al., "A 500MHz Time Digitizer IC with 15.625ps Resolution," ISSCC Dig. Tech. Papers, pp. 58-59, Feb., 1994.