A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 1049-1058

  Zhao, Chong ^a   Bai, Xiaoliang ^a   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGN; CIRCUIT NOISE INTERACTION; RELIABILITY ANALYSIS; SINGLE EVENT UPSET (SEU);

INTEGRATED CIRCUIT TESTING; LOGIC DEVICES; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; SPURIOUS SIGNAL NOISE; TRANSIENTS;

VLSI CIRCUITS;

EID: 33845390781     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584071     Document Type: Conference Paper

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