Post-placement rewiring and rebuffering by exhaustive search for functional symmetries

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 56-63

  Chang, Kai Hui ^a   Markov, Igor L ^a   Bertacco, Valeria ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MODERN CIRCUIT OPTIMIZATIONS; PHASE SHIFT SYMMETRIES; REBUFFERING; REWIRING;

BENCHMARKING; COMPUTATIONAL METHODS; COMPUTER SCIENCE; FORMAL LOGIC; GRAPHIC METHODS; OPTIMIZATION;

COMPUTER AIDED DESIGN;

EID: 33751433608     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560040     Document Type: Conference Paper

References (21)

1. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa and I. L. Markov, "Unification of Partitioning, Floorplanning and Placement", ICCAD, 2004, pp. 550-557.
2. F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, "Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry", IEEE Trans. on CAD, Sep. 2003, pp. 1117-1137.
3. V. Bertacco and M. Damiani, "Boolean Function Representation Based on Disjoint-Support Decompositions", ICCD, Oct. 1996, pp. 27-32.
4. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?", DAC, 2000, pp. 693-698.
5. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Toward CAD-IP Reuse: The MARCO GSRC Bookshelf of Fundamental CAD Algorithms", IEEE Design and Test, May 2002, pp. 72-81.
6. http://vlsicad.eecs.umich.edu/BK/PlaceUtils/
7. C. W. Chang, M. F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C. H. Cheng, and S. J. Chen, "Fast Postplacement Optimization Using Functional Symmetries", IEEE Trans. on CAD, Jan. 2004, pp. 102-118.
8. C. W. Chang and M. Marek-Sadowska, "Single-Pass Redundancy Addition and Removal", ICCAD, Nov. 2001, pp. 606-609.
9. S. C. Chang, L. P. P. P. van Ginneken, and M. Marek-Sadowska, "Circuit Optimization by Rewiring," IEEE Trans. on Computers, Sep. 1999, pp. 962-969.
10. J. Cong and W. Long, "Theory and Algorithm for SPFD-Based Global Rewiring", IWLS, June 2001, pp. 150-155.
11. P. T. Darga, M. H. Liffiton, K. A. Sakallah, and I. L. Markov, "Exploiting Structure in Symmetry Detection for CNF", DAC, 2004, pp. 530-534.
12. N. Eén and N. Sörensson, "An Extensible SAT-solver", Theory and Apps of Satisfiability Testing, SAT, 2003, pp. 502-518.
13. V. N. Kravets and K. A. Sakallah, "Generalized Symmetries in Boolean Functions", ICCAD, 2000, pp. 526-523.
14. V. N. Kravets, "Constructive Multi-Level Synthesis by Way of Functional Properties",Ph. D. Thesis, Univ. of Michigan,2001.
15. A. Mishchenko, "Fast Computation of Symmetries in Boolean Functions", IEEE Trans. on CAD, Nov. 2003, pp. 1588-1593.
16. D. Moller, J. Mohnke, and M. Weber, "Detection of Symmetry of Boolean Functions Represented by ROBDDs", ICCAD, 1993, pp. 680-684.
17. S. Panda, F. Somenzi, and B. F. Plessier, "Symmetry Detection and Dynamic Variable Ordering of Decision Diagrams", ICCAD, 1994, pp. 628-631.
18. D. E. Wallace, "Recognizing input equivalence in digital logic", IWLS, 2001, pp. 207-212.
19. G. Wang, A. Kuehlmann, and A. Sangiovanni-Vincentelli, "Structural Detection of Symmetries in Boolean Functions", ICCD, 2003, pp. 498-503
20. Y. L. Wu, W. Long, and H. Fan, "A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks", International VLSI Design Conference, 2000, pp. 268-273.
21. S. Yamashita, H. Sawada, and A. Nagoya, "A New Method to Express Functional Permissibilities for LUT Based FPGAs and Its Applications", ICCAD, 1996, pp. 254-261.