-
2
-
-
0022769976
-
Graph-based algorithms for boo lean function manipulation
-
August
-
R. E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans, on Computers, C-35(6):677-691, August 1986.
-
(1986)
IEEE Trans, on Computers
, vol.C-35
, Issue.6
, pp. 677-691
-
-
Bryant, R.E.1
-
3
-
-
0005726267
-
Verifying equivalence of functions with unknown input correspondence
-
February
-
D. I. Cheng and M. Marek-Sadowska. Verifying equivalence of functions with unknown input correspondence. In Proc. European Design Automation Conf., pp. 81-85, February 1993.
-
(1993)
Proc. European Design Automation Conf
, pp. 81-85
-
-
Cheng, D.I.1
Marek-Sadowska, M.2
-
4
-
-
0018038632
-
A digital synthesis procedure under function symmetries and mapping methods
-
C. R. Edwards and S. L. Hurst. A digital synthesis procedure under function symmetries and mapping methods. IEEE Trans, on Computers, C-27:985-997, 1978.
-
(1978)
IEEE Trans, on Computers
, vol.C-27
, pp. 985-997
-
-
Edwards, C.R.1
Hurst, S.L.2
-
7
-
-
0033359923
-
Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering
-
July
-
M. C.Hansen, H. Yalcin, and J. P. Hayes. Unveiling the ISCAS- 85 benchmarks: A case study in reverse engineering. IEEE Design and Test of Computers, 16(3):72-80, July 1999.
-
(1999)
IEEE Design and Test of Computers
, vol.16
, Issue.3
, pp. 72-80
-
-
Hansen, M.C.1
Yalcin, H.2
Hayes, J.P.3
-
10
-
-
0026138575
-
Multi level logic synthesis of symmetric switching functions
-
April
-
B.-G. Kim and D. L. Dietmeyer. Multilevel logic synthesis of symmetric switching functions, IEEE Trans, on Computer- Aided Design of Integrated Circuits and Systems, 10(4):436- 446, April 1991.
-
(1991)
IEEE Trans, on Computer- Aided Design of Integrated Circuits and Systems
, vol.10
, Issue.4
, pp. 436-446
-
-
Kim, B.-G.1
Dietmeyer, D.L.2
-
18
-
-
0033078737
-
BDD minimization using symmetries
-
February
-
C. Scholl, D. Moller, P. Molitor, and R. Drechsler BDD minimization using symmetries. IEEE Trans, on Computer-Aided Design of Integrated Circuits, 18(2):81-100, February 1999.
-
(1999)
IEEE Trans, on Computer-Aided Design of Integrated Circuits
, vol.18
, Issue.2
, pp. 81-100
-
-
Scholl, C.1
Moller, D.2
Molitor, P.3
Drechsler, R.4
-
19
-
-
84932847893
-
A symbolic analysis of relay and switching circuits
-
C E. Shannon. A symbolic analysis of relay and switching circuits. AIEE Trans 57:713-723; 1938.
-
(1938)
AIEE Trans
, vol.57
, pp. 713-723
-
-
Shannon, C.E.1
-
20
-
-
0028553475
-
Boolean matching using generalized reed-muller forms
-
June
-
C. C. Tsai and M Marek-Sadowska. Boolean matching using generalized Reed-Muller forms. In Proc. Design Automation Conf., pp. 339-344, June 1994.
-
(1994)
Proc. Design Automation Conf
, pp. 339-344
-
-
Tsai, C.C.1
Marek-Sadowska, M.2
-
21
-
-
0002919769
-
Generalized reed- muller forms as a tool to detect symmetries
-
August
-
C. C. Tsai and M. Marek-Sadowska. Generalized Reed- Muller forms as a tool to detect symmetries. IEEE Trans. on Computers, C-45 (1);772-781, August 1996.
-
(1996)
IEEE Trans. on Computers
, vol.C-45
, Issue.1
, pp. 772-781
-
-
Tsai, C.C.1
Marek-Sadowska, M.2
-
22
-
-
84949918008
-
-
http://www.eecs.umich.edu/-jhayes/iscas/benchmark.html.
-
-
-
|