Fast graph-based alternative wiring scheme for Boolean networks

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 268-273

  Wu, Yu Liang ^a   Long, Wangning ^a   Fan, Hongbing ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; VLSI CIRCUITS;

BOOLEAN NETWORKS; GRAPH BASED ALTERNATIVE WIRING; REDUNDANCY ADDITION AND REMOVAL FOR MULTILEVEL BOOLEAN OPTIMIZATION;

INTEGRATED CIRCUIT TESTING;

EID: 0033872791     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)