Toward CAD-IP reuse: A web bookshelf of fundamental algorithms

IEEE Design and Test of Computers

Volumn 19, Issue 3, 2002, Pages 72-81

  Caldwell, Andrew E ^a   Markov, Igor L ^c   Kahng, Andrew B ^b  

^a Simplex Solutions ^*  (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c University of Michigan   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN-INTELLECTUAL PROPERTY REUSE; DESIGN TECHNOLOGY PRODUCTIVITY;

ALGORITHMS; COMPUTER SOFTWARE; DATA STRUCTURES; DATABASE SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTELLECTUAL PROPERTY; INTERNET; INTEROPERABILITY; REUSABILITY; SOFTWARE ENGINEERING; STANDARDS; VLSI CIRCUITS;

COMPUTER AIDED DESIGN;

EID: 0036575032     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. Hypergraph partitioning for VLSI CAD: Methodology for heuristic development, experimentation and reporting
2. Can recursive bisection alone produce routable placements?
3. VLSI CAD bookshelf
4. Tragic loss or good riddance? The impending demise of traditional scholarly journals
5. ACM/SIGDA design automation benchmarks: Catalyst or anatherma?
6. The ISPD-98 circuit benchmark suite
7. Partitioning benchmarks for the VLSI CAD community
8. Designing and reporting on computational experiments with heuristic methods
9. Procedure for ranking heuristics applied to graph partitioning
10. Cut size statistics of graph bisection heuristics
11. The open source software licensing page
12. The cathedral and the bazaar