Selection of crosstalk-induced faults in enhanced delay test

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 21, Issue 2, 2005, Pages 181-195

  Li, Huawei ^a   Li, Xiaowei ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

Automatic test pattern generation (ATPG); Critical paths; Crosstalk; Delay test

Indexed keywords

ALGORITHMS; BENCHMARKING; CMOS INTEGRATED CIRCUITS; CROSSTALK; MATHEMATICAL MODELS; WAVEFORM ANALYSIS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); BENCHMARK CIRCUITS; CRITICAL PATHS; DELAY TEST;

INTEGRATED CIRCUIT TESTING;

EID: 17444419423     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10836-005-6147-0     Document Type: Article

References (15)

1. 181-195 1. R. Anglada and A. Rubio, "Logic Fault Model for Crosstalk Interferences in Digital Circuits," International Journal of Electronics, vol. 67, no. 3, pp. 423-425, 1989.
2. W. Chen, S.K. Gupta, and M.A. Breuer, "Test Generation in VLSI Circuits for Crosstalk Noise," in Proc. IEEE International Test Conference, 1998, pp. 641-650.
3. W.-Y. Chen, S.K. Gupta, and M.A. Breuer, "Test Generation for Crosstalk-Induced Delay in Integrated Circuits," in Proc. IEEE International Test Conference, 1999, pp. 191-200.
4. W.-Y. Chen, S. K.Gupta, and M.A. Breuer, "Test Generation for Crosstalk-Induced Faults: Framework and Computational Results," Journal of Electronic Testing: Theory and Applications, vol. 18, no. 1, pp. 17-28, 2002.
5. K.-T. Cheng and H.-C. Chen, "Classification and Identification of Nonrobust Untestable Path Delay Faults," IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 15, no. 8, pp. 845-853, 1996.
6. K.-T. Cheng, S. Dey, M. Rodgers, and K. Roy. "Test Challenges for Deep Sub-Micron Technologies," in Proc. 37th Design Automation Conference, 2000, pp. 142-149.
7. Y. Itazaki, Matsumoto, and K. Kinoshita, "An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuit," in Proc. Sixth Asian Test Symposium, 1997, pp. 22-27.
8. K. Keller, H. Takahashi, K. Saluja, and Y. Takamatsu, "On Reducing the Target Fault List of Crosstalk-Induced Delay Faults in Synchronous Sequential Circuits," in Proc. International Test Conference, 2001, pp. 568-577.
9. J.-J. Krstic, Liou, Y.-M. Jiang, and K.-T. Cheng, "Delay Testing Considering Crosstalk-Induced Effects," in Proc. of IEEE International Test Conference, 2001, pp. 558-567.
10. R. Kundu and R.D. Blanton, "Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk," in Proc. of IEEE International Test Conference, 2003.
11. K.T. Lee, C. Nordquist, and J.A. Abraham, "Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits," in Proc. 16th IEEE VLSI Test Symposium, 1998, pp. 34-39.
12. H. Li, Z. Li, and Y. Min, "Reduction of Number of Paths to be Tested in Delay Testing," Journal of Electronic Testing: Theory and Applications, vol. 16, no. 5, pp. 477-485, 2000.
13. Y. Min, Z. Li, and Z. Zhao, "Boolean Process," Science in China, Series E, vol. 40, no. 3, pp. 250-257, 1997.
14. F. Moll and A. Rubio, "Spurious Signals in Digital CMOS VLSI Circuit: A Propagation Analysis," IEEE Tran. on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 39, no. 10, pp. 749-752, 1992.
15. A. Rubio, N. Itazaki, X. Xu, and K. Kinoshita, "An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, pp. 387-394, 1994.