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Volumn 2003-January, Issue , 2003, Pages 178-183

Delay test pattern generation considering crosstalk-induced effects

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; INTEGRATED CIRCUIT TESTING;

EID: 33751117607     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250806     Document Type: Conference Paper
Times cited : (8)

References (11)
  • 3
    • 0024728116 scopus 로고
    • Logic Fault Model for Crosstalk Interferences in Digital Circuits
    • R. Anglada and A. Rubio, "Logic Fault Model for Crosstalk Interferences in Digital Circuits," International Journal of Electronics, Vol. 67, No. 3, pp. 423-425, 1989.
    • (1989) International Journal of Electronics , vol.67 , Issue.3 , pp. 423-425
    • Anglada, R.1    Rubio, A.2
  • 4
    • 0031362121 scopus 로고    scopus 로고
    • An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuit
    • Itazaki, Y. Matsumoto, and K. Kinoshita, "An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuit," Proceedings of Sixth Asian Test Symposium, pp.22-27, 1997.
    • (1997) Proceedings of Sixth Asian Test Symposium , pp. 22-27
    • Itazaki1    Matsumoto, Y.2    Kinoshita, K.3
  • 6
    • 0034512340 scopus 로고    scopus 로고
    • Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
    • W.-Y. Chen, S. K.Gupta, and M.A.Breuer, "Test Generation for Crosstalk-Induced Faults: Framework and Computational Results," Proceedings of ninth Asian Test Symposium, pp. 305-310, 2000.
    • (2000) Proceedings of Ninth Asian Test Symposium , pp. 305-310
    • Chen, W.-Y.1    Gupta, S.K.2    Breuer, M.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.