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Volumn , Issue , 2000, Pages 305-310

Test generation for crosstalk-induced faults: Framework and computational results

Author keywords

[No Author keywords available]

Indexed keywords

MIXED SIGNAL TEST GENERATOR;

EID: 0034512340     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (29)

References (22)
  • 1
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    • Goel, A.K.1    Huang, Y.R.2
  • 2
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    • An approach to crosstalk effect analysis and avoidance techniques in digital CMOS VLSI circuits
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  • 6
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    • An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines
    • A. E. Zain and S. Chowdhury, "An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines", Proc. Int'l Conf. on Computed Aided Design, pp. 443448, 1992.
    • (1992) Proc. Int'l Conf. on Computed Aided Design , pp. 443448
    • Zain, A.E.1    Chowdhury, S.2
  • 7
    • 0027544175 scopus 로고
    • Crosstalk analysis for highspeed pulse propagation in lossy electrical interconnections
    • February
    • S. Voranantakul and J. L. Prince, "Crosstalk analysis for highspeed pulse propagation in lossy electrical interconnections", IEEE Trans, on Components, Hybrids, and Manufacturing Technology, Vol. 16, No. 1, pp. 127-136, February 1993.
    • (1993) IEEE Trans, on Components, Hybrids, and Manufacturing Technology , vol.16 , Issue.1 , pp. 127-136
    • Voranantakul, S.1    Prince, J.L.2
  • 8
    • 0026120433 scopus 로고
    • Crosstalk and transient analysis of highspeed interconnects and packages
    • March
    • H. You and M. Soma, "Crosstalk and transient analysis of highspeed interconnects and packages", IEEE Trans, on Solid State Circuits, Vol. 26, pp. 319-30, March 1991.
    • (1991) IEEE Trans, on Solid State Circuits , vol.26 , pp. 319-330
    • You, H.1    Soma, M.2
  • 9
    • 0025252022 scopus 로고
    • Modeling and simulation of interconnection delays and crosstalk in highspeed integrated circuits
    • January
    • D. S. Gao, A. T. Yang and S. M. Rang, "Modeling and simulation of interconnection delays and crosstalk in highspeed integrated circuits", IEEE Trans, on Circuits and Systems, Vol. 37, pp. 1-9, January 1990.
    • (1990) IEEETrans, on Circuits and Systems , vol.37 , pp. 1-9
    • Gao, D.S.1    Yang, A.T.2    Rang, S.M.3
  • 10
    • 0032316471 scopus 로고    scopus 로고
    • Automatic test pattern generation for crosstalk glitches in digital circuits
    • K. T. Lee, C. Nordquist and J. A. Abraham "Automatic test pattern generation for crosstalk glitches in digital circuits", Proc. VLSI Test Symposium, pp. 34-39, 1998.
    • (1998) Proc. VLSI Test Symposium , pp. 34-39
    • Lee, K.T.1    Nordquist, C.2    Abraham, J.A.3
  • 11
    • 0000670599 scopus 로고
    • Methodology of detection of spurious signals in VLSI circuits
    • F. Moll and A. Rubio, "Methodology of detection of spurious signals in VLSI circuits", Proc. Europe Test Conference, pp. 491-496, 1993.
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    • Moll, F.1    Rubio, A.2
  • 12
    • 0032306411 scopus 로고    scopus 로고
    • Test generation in VLSI circuits for crosstalk noise
    • W. Y. Chen, S. K. Gupta and M. A. Breuer, "Test generation in VLSI circuits for crosstalk noise", Proc. Int'l Test Conf., pp. 641-650, 1998.
    • (1998) Proc. Int'l Test Conf , pp. 641-650
    • Chen, W.Y.1    Gupta, S.K.2    Breuer, M.A.3
  • 15
    • 0030143091 scopus 로고    scopus 로고
    • Inductance and capacitance formulas for VLSI interconnects
    • May
    • N. Delorme, M. Bellevile and J. Chilo, "Inductance and capacitance formulas for VLSI interconnects". Electronic Letters, Vol. 32, No. 11, pp. 996-997, May 1996.
    • (1996) Electronic Letters , vol.32 , Issue.11 , pp. 996-997
    • Delorme, N.1    Bellevile, M.2    Chilo, J.3
  • 16
    • 0031354479 scopus 로고    scopus 로고
    • Analytic models for crosstalk delay and pulse analysis for non-ideal inputs
    • W. Y. Chen, S. K. Gupta and M. A. Breuer, "Analytic models for crosstalk delay and pulse analysis for non-ideal inputs", Proc. Int'l Test Conf., pp. 809-818, 1997.
    • (1997) Proc. Int'l Test Conf , pp. 809-818
    • Chen, W.Y.1    Gupta, S.K.2    Breuer, M.A.3
  • 20
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    • An implicit enumeration algorithm to generate tests for combinational logic circuits
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    • Goel, P.1
  • 22
    • 0033316674 scopus 로고    scopus 로고
    • Test generation for crosstalk-induced delay in integrated circuits
    • W. Y. Chen. S. K. Gupta and M. A. Breuer, "Test generation for crosstalk-induced delay in integrated circuits", Proc. Int'l Test Conf., pp. 191-200, 1999.
    • (1999) Proc. Int'l Test Conf , pp. 191-200
    • Chen. S K Gupta, W.Y.1    Breuer, M.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.