On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 568-577

  Keller, Keith J ^a   Takahashi, Hiroshi ^b   Saluja, Kewal K ^a   Takamatsu, Yuzo ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMBINATORIAL CIRCUITS; CROSSTALK; INTEGRATED CIRCUIT TESTING; SYNCHRONIZATION;

DELAY FAULTS; TIMING INFORMATIONS;

SEQUENTIAL CIRCUITS;

EID: 0035687593     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966675     Document Type: Article

References (8)

1. A fault simulator method for crosstalk faults in synchronous sequential circuits
2. Analytic method for crosstalk delay and pulse analysis under non-ideal inputs
3. Test generation in VLSI circuits for crosstalk noise
4. Test generation for crosstalk-induced delay in integrated circuits
5. Test generation for crosstalk-induced delay faults: Framework and computational results
6. Generating tests for delay faults in nonscan circuits
7. Techniques for crosstalk avoidance in the physical design of high-performance digital systems
8. Switching window computation for static timing analysis in presence of crosstalk noise