Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 122-130

  Kundu, Rahul ^a   Blanton, R D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CROSSTALK; DELAY CIRCUITS;

TEST VECTORS;

LOGIC CIRCUITS;

EID: 0142184830     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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