False timing path identification using ATPG techniques and Delay-Based information

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 562-565

  Zeng, Jing ^a   Abadir, Magdy ^a   Abraham, Jacob ^b  

^a MOTOROLA INC   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

ATPG; False timing paths; Static timing analysis; Timing slack

Indexed keywords

STATIC TIMING ANALYSIS;

DELAY CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; TIMING CIRCUITS;

VLSI CIRCUITS;

EID: 0036044556     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012688     Document Type: Article

References (9)

1. Functional timing analysis using ATPG
2. Timing analysis with known false sub-graphs
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4. VIPER: An efficient vigorously sensitizable path extractor
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6. A quick and inexpensive method to identify false critical paths using ATPG techniques: An experiment with a PowerPC microprocessor
7. Detecting false tuning paths: Experiments on PowerPC(TM) microprocessors
8. Tinting analysis based on primitive path delay fault identification
9. Full chip false timing path identification: Applications to the PowerPC microprocessors