Logic design for on-chip test clock generation implementation details and impact on delay test quality

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 56-61

  Beck, Matthias ^a   Barondeau, Olivier ^a   Kaibel, Martin ^a   Poehl, Frank ^a   Lin, Xijiang ^b   Press, Ron ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC; LOGIC DESIGN; TESTING;

DELAY TEST QUALITY; ON-CHIP CLOCK GENERATION; SYSTEM-ON-CHIP;

MICROPROCESSOR CHIPS;

EID: 33646944417     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.199     Document Type: Conference Paper

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