On the automation of the test flow of complex SoCs

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 166-171

  Appelle, D ^a   Tancorre, V ^a   Bernardi, P ^b   Grosso, M ^b   Rebaudengo, M ^b   Reorda, M Sonza ^b  

^a STMICROELECTRONICS   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER SOFTWARE; MACHINE TOOLS; MICROPROCESSOR CHIPS; SILICON;

ATE-READABLE FORMAT; CORE-LEVEL TEST STRUCTURE; SYSTEMS-ON-CHIP (SOC); TEST APPLICATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 33751092311     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.51     Document Type: Conference Paper

References (16)

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