A hierarchical infrastructure for SoC test management

IEEE Design and Test of Computers

Volumn 20, Issue 4, 2003, Pages 32-39

  Benso, Alfredo ^a   Di Carlo, Stefano ^a   Prinetto, Paolo ^a   Zorian, Yervant ^b  

^a POLITECNICO DI TORINO   (Italy)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL LIBRARIES; INTERFACES (COMPUTER); NETWORK PROTOCOLS; SCHEDULING; SYSTEMS ANALYSIS;

TEST BLOCK; TEST CONTROL BUS; TEST MANAGEMENT; TEST STRUCTURE CONFIGURATION;

BUILT-IN SELF TEST;

EID: 0042021943     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1214350     Document Type: Article

References (0)