Energy- and time-efficient matrix multiplication on FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 11, 2005, Pages 1305-1318

  Jang, Ju Wook ^a,b   Choi, Seonil B ^a,c   Prasanna, Viktor K ^a,d  

^a IEEE   (South Korea)

^b Sogang University   (South Korea)

^c INTEL CORPORATION   (United States)

^d University of Southern California ^*  (United States)

Author keywords

Algorithm design; Configurable hardware; Energy delay tradeoff; Field programmable gate array (FPGA); Linear array; Matrix multiplication; Performance estimation

Indexed keywords

ALGORITHM DESIGN; CONFIGURABLE HARDWARE; ENERGY DELAY TRADEOFF; LINEAR ARRAYS; MATRIX MULTIPLICATION; PERFORMANCE ESTIMATION;

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC LOSSES; FUNCTION EVALUATION; LOGIC DESIGN; MATRIX ALGEBRA;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33750919950     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.859562     Document Type: Article

References (27)

1. A. Amira, A. Bouridane, and P. Milligan, "Accelerating matrix product on reconfigurable hardware for signal processing," in Proc. 11th Int. Conf. Field-Programmable Logic and Its Applications (FPL), 2001, pp. 101-111.
2. B. Bass, "A low-power, high-performance, 1024-point FFT processor," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 380-387, Mar. 1999.
3. J. Becker, T. Pionteck, and M. Glesner, "DReAM: A dynamically reconfigurable architecture for future mobile communication applications," in Proc. Field-Programmable Logic and Its Applications (FPL), 2002, pp. 312-321.
4. BenPRO Virtex TM-II Pro DIME-II Module [Online]. Available: http://www.nallatech.com/solutions/products/embedded_systems/dime2/rc_modules/ benpro/
5. A. Bogliolo, L. Benini, and G. Micheli, "Regression-based RTL power modeling," ACM Trans. Des. Automat. Electron. Syst., vol. 5, no. 3, pp. 337-372, 2000.
6. B. L. Bowerman and R. T. O'Connell, Linear Statistical Models - An Applied Approach, 2nd ed. Pacific Grove, CA: Brooks/Cole, 1990.
7. G. Brebner and N. Bergman, "Reconfigurable computing in remote and harsh environments," in Proc. Field-Programmable Logic and Its Applications (FPL), 1999, pp. 195-204.
8. S. Choi, J.-W. Jang, S. Mohanty, and V. K. Prasanna, "Domain- specific modeling for rapid energy estimation of reconfigurable architectures," J. Supercomputing, vol. 26, no. 3, pp. 259-281, Nov. 2003.
9. S. Choi, R. Scrofano, V. K. Prasanna, and J.-W. Jang, "Energy efficient signal processing using FPGAs," in Proc. Field Programmable Gate Array (FPGA), 2003, pp. 225-234.
10. S. Choi, G. Govindu, J.-W. Jang, and V. K. Prasanna, "Energy- efficient and parameterized designs of fast fourier transforms on FPGAs," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing (ICASSP), vol. 2, 2003, pp. 521-524.
11. O. D. Fidanci, D. Poznanovic, K. Gaj, T. El-Ghazawi, and N. Alexandridis, "Performance and overhead in a hybrid reconfigurable computer," in Proc. Reconfigurable Architecture Workshop (RAW), 2003, pp. 176-183.
12. J. Frigo, M. Gokhale, and D. Lavenier, "Evaluation of the streams-C C-to-FPGA compiler: An applications perspective," Proc. Field Programmable Gate Arrays (FPGA), pp. 134-140, 2001.
13. R. Hogg and E. Tanis, Probability and Statistical Inference, 6th ed. Upper Saddle River, NJ: Prentice-Hall, 2001, pp. 656-657.
14. J.-W. Jang, S. Choi, and V. K. Prasanna, "Energy efficient matrix multiplication on FPGAs," Proc. Field-Programmable Logic and Its Applications (FPL), pp. 534-544, 2002.
15. H. T. Rung and C. E. Leiserson, "Systolic arrays for (VLSI)," Introduction to VLSI Systems, 1980.
16. W. J. C. Melis, P. Y. K. Cheung, and W. Luk, "Image registration of real-time broadcast video using the UltraSONIC reconfigurable computer," Proc. Field Programmable Logic and Its Applications (FPL), pp. 1148-1151, 2002.
17. O. Mencer, M. Morf, and M. J. Flynn, "PAM-Blox: High performance FPGA design for adaptive computing," in Field-Programmable Custom Computing Machines (FCCM), 1998, pp. 167-174.
18. P. Master and P. M. Athanas, "Reconfigurable computing offers options for 3G," Wireless Syst. Des., vol. 4, no. 1, pp. 20-27, 1999.
19. ML310 Virtex-II Pro Development Platform [Online]. Available: http://www.xilinx.com/univ/ML310/ml310_mainpage.html
20. Model-Based Integrated Simulation [Online]. Available: http://milan.usc.edu
21. W. Najjar, W. Böhm, B. Draper, J. Hammes, R. Rinker, R. Beveridge, M. Chawathe, and C. Ross, "From algorithms to hardware - A high-level language abstraction for reconfigurable computing," in Proc. IEEE Computer, vol. 36, Aug. 2003, pp. 63-69.
22. V. K. P. Kumar and Y. Tsai, "On synthesizing optimal family of linear systolic arrays for matrix multiplication," IEEE Trans. Comput., vol. 40, no. 6, pp. 770-774, 1991.
23. R. Scrofano, J.-W. Jang, and V. K. Prasanna, "Energy-Efficient discrete cosine transform on FPGAs," in Proc. Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 215-221.
24. L. Shang, A. Kaviani, and K. Bathala, "Dynamic power consumption in Virtex-II FPGA family," in Proc. Field-Programmable Gate Arrays (FPGA), 2002, pp. 157-164.
25. N. Srivastava, J. L. Trahan, R. Vaidyanathan, and S. Rai, "Adaptive image filtering using run-time reconfiguration," in Proc. Reconfigurable Architectures Workshop (RAW), 2003.
26. Xilinx Application Note: Virtex-II Series and Xilinx ISE 4.1i Design Environment (2001). [Online]. Available: http://www.xilinx.com
27. XPower [Online]. Available: http://toolbox.xilinx.com/docsan/xilinx5/ help/xpower/html/b_getting_started/b_overview.htm