Accelerating matrix product on reconfigurable hardware for signal processing

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2147, Issue , 2001, Pages 101-111

  Amira, Abbes ^a   Bouridane, Ahmed ^a   Milligan, Peter ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY LOCK LOOPS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SIGNAL PROCESSING; TREES (MATHEMATICS);

BLOCK RAMS; DIGITAL DELAY-LOCKED LOOPS; MATRIX MULTIPLICATION ALGORITHM; MATRIX PRODUCTS; MULTIPLY-AND-ACCUMULATE; PRELIMINARY PERFORMANCE RESULTS; PROPOSED ARCHITECTURES; WALLACE TREE;

RECONFIGURABLE HARDWARE;

EID: 84949199736     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44687-7_11     Document Type: Conference Paper

References (9)

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