Dynamic power consumption in virtex™-II FPGA family

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2002, Pages 157-164

  Shang, Li ^a   Kaviani, Alireza S ^a   Bathala, Kusuma ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POWER MEASUREMENT; INTERCONNECTION NETWORKS; SWITCHING CIRCUITS;

FIELD PROGRAMMABLE DEVICES (FPD);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036384096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/503048.503072     Document Type: Conference Paper

References (8)

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3. A. Gracia, "Power consumption and optimization in field programmable gate arrays," Ph.D. thesis, Département Communications et Électronique, Ecole Nationale Supérieure des Télécommunications, 2000.
4. th Int. Wksp. Embedded/Distributed HPC Systems and Applications," pp. 776-783, May 2000.
5. Xilinx Inc., "Virtex-II Platform FPGA Handbook," 2000.
6. Gary Yeap, "Practical Low Power Digital VLSI Design," Kluwer Academic Publishers, 1998.
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8. A. Shen, et. al, "On average power dissipation and random pattern testability of CMOS Combinational Logic Networks," IEEE ICCAD, pp. 402-407, 1992.