Impact of instruction-level parallelism on multiprocessor performance and simulation methodology

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1997, Pages 72-83

  Pai, Vijay S ^a   Ranganathan, Parthasarathy ^a   Adve, Sarita V ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS;

INSTRUCTION LEVEL PARALLELISM (ILP);

PARALLEL PROCESSING SYSTEMS;

EID: 0030737826     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)