A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2566-2576

  Byun, Sangjin ^b   Lee, Jyung Chan ^b   Shim, Jae Hoon ^a,b   Kim, Kwangjoon ^a,b   Yu, Hyun Kyu ^a,b  

^a IEEE

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Clock and data recovery; CMOS integrated circuits; Demultiplexer; OC 192; Quarter rate linear phase detector; SONET

Indexed keywords

BINARY SEQUENCES; BIT ERROR RATE; DATA REDUCTION; DETECTORS; ELECTRIC POWER UTILIZATION; OSCILLATORS (ELECTRONIC); VOLTAGE CONTROL;

CLOCK AND DATA RECOVERY; QUARTER-RATE LINEAR PHASE DETECTORS; SONET;

CMOS INTEGRATED CIRCUITS;

EID: 33750830682     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.883334     Document Type: Conference Paper

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