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Volumn 39, Issue 12, 2004, Pages 2349-2358

A 10-GB/s SONET-compliant CMOS transceiver -With low crosstalk and intrinsic jitter

Author keywords

Clock and data recovery; CMOS integrated circuits; Crosstalk; Integrated inductors; Jitter; OC 192; Phase locked loops; SONET; Transceivers; Voltage controlled oscillators

Indexed keywords

CROSSTALK; ELECTRIC INDUCTORS; JITTER; PHASE LOCKED LOOPS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

EID: 10444268061     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.835652     Document Type: Conference Paper
Times cited : (13)

References (8)
  • 1
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    • A fully integrated SiGe receiver IC for 10 Gb/s data rate
    • Dec.
    • Y. Greshishchev et al., "A fully integrated SiGe receiver IC for 10 Gb/s data rate," IEEE J. Solid-State Circuits, pp. 1949-1957, Dec. 2000.
    • (2000) IEEE J. Solid-state Circuits , pp. 1949-1957
    • Greshishchev, Y.1
  • 2
    • 0036105959 scopus 로고    scopus 로고
    • OC-192 receiver in standard 0.18 μm CMOS
    • Feb.
    • J. Cao et al., "OC-192 receiver in standard 0.18 μm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 250-251.
    • (2002) ISSCC Dig. Tech. Papers , pp. 250-251
    • Cao, J.1
  • 3
    • 84893766337 scopus 로고    scopus 로고
    • A 2 GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6° phase error
    • Sept.
    • P. Andreani, "A 2 GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6° phase error," in Proc. ESSCIRC, Sept. 2002, pp. 815-818.
    • (2002) Proc. ESSCIRC , pp. 815-818
    • Andreani, P.1
  • 4
    • 0343897881 scopus 로고    scopus 로고
    • A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers
    • Dec.
    • E. Säckinger and W. C. Fischer, "A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers," IEEE J. Solid-State Circuits, vol. 35, pp. 1884-1888, Dec. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1884-1888
    • Säckinger, E.1    Fischer, W.C.2
  • 6
    • 0026999466 scopus 로고
    • A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s
    • Dec.
    • A. Pottbacker et al., "A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s," IEEE J. Solid-State Circuits, vol. 27, pp. 1747-1751, Dec. 1992.
    • (1992) IEEE J. Solid-state Circuits , vol.27 , pp. 1747-1751
    • Pottbacker, A.1
  • 7
    • 0037321173 scopus 로고    scopus 로고
    • A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator
    • Feb.
    • H. Nosaka et al., "A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator." IEEE J. Solid-State Circuits, vol. 38, pp. 192-197, Feb. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , pp. 192-197
    • Nosaka, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.