A current-mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2003, Pages 4-7

  Hemati, Saied ^a   Banihashemi, Amir H ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CASCODE CONFIGURATION; CMOS TECHNOLOGY; CURRENT MODE; HIGH-PRECISION; ITERATIVE DECODER; LOW VOLTAGES; LOW-VOLTAGE; MIN-SUM; SHORT CHANNEL MOSFETS; SIMULATION RESULT; SOFT COMPUTING APPLICATIONS; VOLTAGE REQUIREMENT; WINNER TAKE ALLS; WINNER-TAKE-ALL CIRCUITS;

CMOS INTEGRATED CIRCUITS; DECODING; SOFT COMPUTING;

NAVIGATION SYSTEMS; CMOS INTEGRATED CIRCUITS;

EID: 77956051093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1301962     Document Type: Conference Paper

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