Full CMOS min-sum analog iterative decoder

IEEE International Symposium on Information Theory - Proceedings

Volumn , Issue , 2003, Pages 347-

  Hemati, Saied ^a   Banihashemi, Amir H ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; MULTIPLYING CIRCUITS; SIGNAL TO NOISE RATIO; TURBO CODES;

ANALOG ITERATIVE DECODER; DIGITAL MULTIPLIERS; HAMMING CODE; LOW-DENSITY PARITY-CHECK CODES;

DECODING;

EID: 0142008240     PISSN: 21578096     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isit.2003.1228362     Document Type: Conference Paper

References (8)

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7. F. Zarkeshvari, and A. H. Banihashemi, "On implementation of min-sum algorithm for decoding low-density parity-check (LDPC) codes," IEEE Globecom Conf. 2002, Taipei, Taiwan, Nov. 2002.
8. J. Chen, and M. P. C. Fossoreir, "Density evolution for two improved BP-based decoding algorithms of LDPC codes," IEEE Comm. Lett., vol. 6, no. 5, pp. 208-210, May 2002.