Influence of gate patterning on line edge roughness

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 21, Issue 6, 2003, Pages 3140-3143

  Leunissen, Leonardus H A ^a   Jonckheere, Rik ^a   Ronse, Kurt ^a   Derksen, Giljam B ^b  

^a IMEC   (Belgium)

^b TNO   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; DIFFRACTION; ELECTRON BEAM LITHOGRAPHY; ETCHING; POLYSILICON; SCANNING ELECTRON MICROSCOPY;

LINE EDGE ROUGHNESS (LER); LINEWIDTH ROUGHNESS (LWR);

GATES (TRANSISTOR);

EID: 0942267514     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.1627799     Document Type: Conference Paper

References (4)

1. ITRS Roadmap, 2001 edition
2. M. Ercken et al., "Line edge roughness and its increasing importance," in Proceedings of the Interface 2002 (unpublished).
3. J. A. Croon et al., "Line edge roughness: Characterization, modeling, and impact on device behavior," Proc. of IEDM, 2002 (unpublished).
4. J. A. Croon et al., "Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield," ESSDERC (to be published).