Vectorless estimation of maximum instantaneous current for sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 11, 2006, Pages 2341-2352

  Hsieh, Cheng Tao ^a,b   Lin, Jian Cheng ^c   Chang, Shih Chieh ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c SpringSoft Inc   (Taiwan)

Author keywords

Maximum instantaneous current (MIC); Sequential logic circuits; Signal correlation; Very large scale integration (VLSI)

Indexed keywords

MAXIMUM INSTANTANEOUS CURRENT (MIC); SEQUENTIAL LOGIC CIRCUITS; SIGNAL CORRELATION;

ALGORITHMS; GRAPH THEORY; PARAMETER ESTIMATION; SWITCHING; VLSI CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 33750599455     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.873894     Document Type: Article

References (24)

1. J. Benkoski, E. Vanden Meersch, L. J. M. Claesen, and H. De Man, "Timing verification using statically sensitizable paths," IEEE Trans. Comput.-Aided Des. Integr. Circuirs Syst., vol. 9, no. 10, pp. 1073-1084, Oct. 1990.
2. S. Bobba and I. N. Hajj, "Estimation of maximum current envelope for power bus analysis and design," in Proc. ISPD, Apr. 6-8, 1998, pp. 141-146.
3. _, "Estimation of maximum switching activity in digital VLSI circuits," in Proc. Midwest Symp. Circuits Syst., Sacramento, CA, Aug. 3-6, 1997, pp. 1130-1133.
4. S. Busygin, "A new trust region technique for the maximum weight clique problem," a manuscript submitted to Special Issue of Applied Discrete Mathematics: Combinatorial Optimization, 2002. [Online]. Available: http://www.busygin.dp.ua/npc.html
5. S. C. Chang, M. Marek-Sadowska, and K. T. Cheng, "Perturb and simplify: Multi-level Boolean network optimizer," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 15, no. 12, pp. 1494-1504, Dec. 1996.
6. S. C. Chang, K. T. Cheng, N. S. Woo, and M. Marek-Sadowska, "Post layout logic restructuring using alternative wires," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 6, pp. 587-596, Jun. 1997.
7. S. C. Chang, L. V. Ginneken, and M. Marek-Sadowska, "Circuit optimizations by rewiring," IEEE Trans. Comput., vol. 48, no. 9, pp. 962-970, Sep. 1999.
8. H. C. Chen and D. H.-C. Du, "Path sensitization in critical path problem," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 12, no. 2, pp. 196-207, Feb. 1993.
9. S. Chowdhury and J. S. Barkatullah, "Estimation of maximum current in MOS IC logic circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 6, pp. 642-654, Jun. 1990.
10. S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 11, no. 3, pp. 373-383, Mar. 1992.
11. A. Glebov, S. Gavrilov, D. Blaauw, S. Sirichotiyakul, C. Oh, and V. Zolotov, "False-noise analysis using logic implications," in Proc. ICCAD, 2001, pp. 515-521.
12. A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov, R. Randa, and C. Oh, "False-noise analysis using resolution method," in Proc. ISQED, 2002, pp. 437-442.
13. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "K2: An estimator for peak sustainable power of VLSI circuits," in Proc. ISLPED, Aug. 1997, pp. 178-183.
14. Y. M. Jiang, K. T. Cheng, and A. Krstic, "Estimation of maximum power and instantaneous current using a genetic algorithm," in Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 135-138.
15. Y. M. Jiang, A. Krstic, and K. T. Cheng, "Estimation for maximum instantaneous current through supply lines for CMOS circuits," IEEE Trans. VLSI Syst., vol. 8, no. 1, pp. 61-73, Feb. 2000.
16. H. Kriplani, F. Najm, and I. N. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 14, no. 8, pp. 998-1012, Aug. 1995.
17. K. N. Lam and S. Devadas, "PECS: A peak current and power simulator for CMOS combinational circuits," in Proc. IEEE Int. Symp. Circuits Syst., May 1996, pp. 488-491.
18. T. Murayama, K. Ogawa, and H. Yamaguchi, "Estimation of peak current through CMOS VLSI circuit supply lines," in Proc. ASP-DAC, Jan. 1999, pp. 295-298.
19. S. Perremans, L. Claesen, and H. De Man, "Static timing analysis of dynamically sensitizable paths," in Proc. DAC, 1989, pp. 568-573.
20. C.-C. Teng, A. M. Hill, and S.-M. Kang, "Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits," in Proc. IEEE/ACM Int. Conf. CAD, 1995, pp. 366-370.
21. C.-Y. Wang and K. Roy, "Maximum power estimation for CMOS circuits using deterministic and statistic approaches," in Proc. 9th Int. Conf. VLSI Des., Jan. 1995, pp. 364-369.
22. _, "Maximization of power dissipation in large CMOS circuits considering spurious transitions," IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 47, no. 4, pp. 483-490, Apr. 2000.
23. C.-Y. Wang, K. Roy, and T. -L. Chou, "Maximum power estimation for sequential circuits using a test generation based technique," in Proc. IEEE Custom Integr. Circuits Conf., Apr. 1996, pp. 229-232.
24. C. T. Hsieh, VLSI/CAD Lab Page. [Online]. Available: http://nthucad.cs. nthu.edu.tw/~sclab/