Perturb and simplify: multilevel boolean network optimizer

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1494-1504

  Chang, Shih Chieh ^a   Marek Sadowska, Malgorzata ^a   Cheng, Kwang Ting ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; HEURISTIC METHODS; ITERATIVE METHODS; LOGIC GATES; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; PERTURBATION TECHNIQUES; WIRE;

AUTOMATIC TEST PATTERN GENERATION; LOGIC OPTIMIZATION TECHNIQUES; TRANSDUCTION METHOD;

NETWORKS (CIRCUITS);

EID: 0030379797     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552082     Document Type: Article

References (19)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: IEEE Press, 1990.
2. K. A. Bartlett et al., "Multilevel logic minimizing using implicit don't cares," IEEE Trans. Computer-Aided Design, vol. 7, pp. 723-740, June 1988.
3. C. L. Berman and L. H. Trevillyan. "Global flow optimization in automatic logic design," IEEE Trans. Computer-Aided Design, vol. 10, pp. 557-564, May 1991.
4. D. Bostick, G. D. Hachtel, R. Jacoby, M. R. Lightner, P. Moceyunas, C. R. Morrison, and D. Ravenscroft, "The boulder optimal logic design system," in Proc. ICCAD, Nov. 1987, pp. 62-65.
5. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: Multi-level interactive logic optimization system," IEEE Trans. Computer-Aided Design, vol. 6, pp. 1062-1081, Nov. 1989.
6. S. C. Chang, K.-T. Cheng, N.-S. Woo, and M. Marek-Sadowska, "Layout driven logic synthesis for FPGA," in Proc. DAC, June 1994, pp. 308-313.
7. S. C. Chang and M. Marek-Sadowska, "Perturb and simplify: Multi-level Boolean network optimizer," in Proc. ICCAD, Nov. 1994, pp. 2-A.
8. K. T. Cheng and L. A. Entrena, "Multi-level logic optimization by redundancy addition and removal," in Proc. Europ. Conf. Design Au-tomation, Feb. 1993, pp. 373-377.
9. H. Cho, G. D. Hachtel, E. Macii, B. Pleasier, and F. Somenzi, "Algorithms for approximate FSM traversal," in Proc. Europ. Design Automation Conf.. Feb. 1993, pp. 200-204.
10. M. Damiani, J. C. Y. Yang, and G. De Micheli, "Optimization of combinational logic circuits based on compatible gates," in Proc. DAC, June 1993, pp. 631-636.
11. L. A. Entrena and K. T. Cheng, "Sequential logic optimization by redundancy addition and removal," in Proc. ICCAD, Nov. 1993, pp. 310-315.
12. E. Detjens, G. Gannot, R. Rudell, A. L. Sangiovanni-Vincentelli, and A. Wang, "Technology mapping in MIS," in Proc. ICCAD, Nov. 1987, pp. 116-119.
13. J. W. Gault, J. P. Robinson, and S. M. Reddy, "Multiple fault detection in combinational networks," IEEE Trans. Computer, vol C-21, pp. 31-37, Jan. 1972.
14. M. Higashida, J. Ishikawa, M. Hiramine, and K. Nomura, "Multilevel logic optimization based on pseudo maximum sets of permissible functions," in Proc. Euro. Design Automation Conf., Feb. 1993, pp. 386-391.
15. T. Kirkand and M. R. Mercer, "A topological search algorithm for ATPG," in Proc. DAC, June 1987, pp. 502-508.
16. W. Kunz and D. K. Pradhan, "Recursive learning: An attractive alternative to the decision tree for test generation for digital circuits," in Proc. Int. Test Conf., Oct. 1992, pp. 816-825.
17. C. E. Leiserson, F. M. Rose, and J. B. Saxe, "Optimizing synchronous circuit by retiming," in Proc. Third Caltech Conf. VLSI, 1983, pp. 87-116.
18. S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, "The transduction method-design of logic networks based on permissible functions," IEEE Trans. Comput., vol. 38, pp. 1404-1424, Oct. 1989.
19. M. Schulz and E. Auth, "Advanced automatic test pattern generation and redundancy identification techniques," in Proc. Fault Tolerant Computing Symp., June 1988, pp. 30-34.