Maximum power estimation for sequential circuits using a test generation based technique

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1996, Pages 229-232

  Wang, Chuan Yu ^a   Roy, Kaushik ^a   Chou, Tan Li ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC CURRENTS; ENERGY DISSIPATION; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; SEQUENTIAL CIRCUITS; VECTORS;

AUTOMATIC TEST GENERATION; RANDOM SIMULATION BASED TECHNIQUES; STATE TRANSITION GRAPH;

CMOS INTEGRATED CIRCUITS;

EID: 0029723060     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)