A new ADPLL architecture dedicated to program clock references synchronization

International Journal of Electronics

Volumn 93, Issue 12, 2006, Pages 843-861

  Mannino, C ^a   Rabah, H ^a   Weber, S ^a   Tanougast, C ^a   Berviller, Y ^a   Janiaut, M ^a  

^a UNIVERSITÉ DE LORRAINE   (France)

Author keywords

All digital phase locked loop; DVB T; Frequency synthesizer; Jitter; Program clock reference

Indexed keywords

DECODING; FREQUENCY SYNTHESIZERS; JITTER; PHASE SHIFT; SYNCHRONIZATION;

ALL DIGITAL PHASE LOCKED LOOP; DVB-T; PROGRAM CLOCK REFERENCE;

PHASE LOCKED LOOPS;

EID: 33750575628     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207210600900423     Document Type: Article

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