FPGA implementation of a novel all digital PLL architecture for PCR related measurements in DVB-T

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 1027-1031

  Mannino, Christian ^a   Rabah, Hassan ^a   Tanougast, Camel ^a   Berviller, Yves ^a   Janiaut, Michael ^a   Weber, Serge ^a  

^a INSTITUT JEAN LAMOUR   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; DECODING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); JITTER; MOTION PICTURE EXPERTS GROUP STANDARDS; PASSIVE FILTERS; PHASE LOCKED LOOPS;

ALL-DIGITAL PLL; AUDIO AND VIDEO; EMBEDDED PROCESSORS; FPGA IMPLEMENTATIONS; PHASE LOCK LOOP (PLL); PROGRAM CLOCK REFERENCES; QOS MEASUREMENT; TRANSPORT STREAMS;

DIGITAL VIDEO BROADCASTING (DVB);

EID: 84947906823     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_120     Document Type: Conference Paper

References (7)

1. ETSI: Digital Video Broadcasting (DVB); Measurement guidelines for DVB systems. Digital Video Broadcasting, http://www.etsi.org (2001)
2. Hwang, I., Song, S., Kim, S.: A Digitally Controlled Phase-Locked Loop With a Digital Phase-Frequency Detector for Fast Acquisition. IEEE Journal of Solid-State Circuits Vol. 36, No. 10 (2001)
3. Noro, R.: Synchronisation over packet-switching network: theory and applications. Ph. D., EPFL, Lausanne (2000)
4. Olsson, T., Nilsson, P.: An All-Digital PLL Clock Multiplier. Proceeding IEEE Asia- Pacific Conference on ASIC (2002)
5. Mannino, C., Rabah, H., Tanougast, C., Berviller, Y., Weber, S.: Conception d’une architecture dediee à l’instrumentation pour la mesure de gigue en DVB-T. Colloque Interdisciplinaire en Instrumentation, ISBN 2-7462-0828-8, T.1 - pp. 281-288 (2004)
6. SystemC: Version 2, User’s Guide. www.systemc.org (2002)
7. Nepsys: Nepsys Version 1.0, User’s Guide. Prosilog, http://www.prosilog.com (2002)