A turbo-decoding message-passing algorithm for sparse parity-check matrix codes

IEEE Transactions on Signal Processing

Volumn 54, Issue 11, 2006, Pages 4376-4392

  Mansour, Mohammad M ^a  

^a AMERICAN UNIVERSITY OF BEIRUT   (Lebanon)

Author keywords

Iterative decoding; Low density parity check (LDPC) codes; Ramanujan graphs; Repeat accumulate (RA) codes; Turbo decoding algorithm; Very large scale integration (VLSI) decoder architectures

Indexed keywords

ALGORITHMS; ERROR CORRECTION; GRAPH THEORY; ITERATIVE METHODS; SIGNAL TO NOISE RATIO; TURBO CODES; VLSI CIRCUITS;

ITERATIVE DECODING; LOW-DENSITY PARITY-CHECK (LDPC) CODES; RAMANUJAN GRAPHS; REPEAT-ACCUMULATE (RA) CODES; SPARSE PARITY-CHECK MATRIX (SPCM) CODES; TURBO-DECODING MESSAGE-PASSING (TDMP) ALGORITHM;

DECODING;

EID: 33750387049     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2006.880240     Document Type: Article

References (45)

1. M. M. Mansour and N. R. Shanbhag, "Turbo decoder architectures for low-density parity-check codes," in Proc. IEEE Global Telecommunications Conf. (IEEE GLOBECOM), Taipei, Taiwan, Nov. 2002, pp. 1383-1388.
2. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo codes," in IEEE Int. Conf. Communications (ICC), 1993, pp. 1064-1070.
3. R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, 1963.
4. D. Divsalar, H. Jin, and R. J. McEliece, "Coding theorems for turbo-like codes," in Proc. 36th Allerton Conf. Communications, Control, Computing, Sep. 1998, pp. 201-210.
5. H. Jin, A. Khandekar, and R. J. McEliece, "Irregular repeat-accumulate codes," in Proc. 2nd Int. Conf. Turbo Codes Related topics, Brest, France, Sep. 2000, pp. 1-8.
6. S. Lin and D. Costello, Error Control Coding, 2nd ed. Upper Saddle River, NJ: Pearson Prentice-Hall, 2004.
7. Digital Video Broadcasting (DVB-S2) via Satellite [Online].Available: [Online]. Available: http://www.dvb.org.
8. B. Bangerter, "High-throughput wireless LAN air interface," Intel Technol. J., vol. 7, no. 3, Aug. 2003 [Online]. Available: [Online]. Available: http://www.intel.com/technology/itj.
9. Y. Rashi, "LDPC: Efficient alternative FEC for the TFI-OFDM PHY proposal," IEEE 802.15 Working Group for WPAN [Online]. Available: [Online]. Available: http://grouper.ieee.org/groups/802/15/pub.
10. J. Fan, "LDPC: Efficient alternative FEC for the TFI-OFDM PHY proposal," EEE 802.20 Mobile Broadband Wireless Access (MBWA) [Online]. Available: [Online]. Available: http://grouper.ieee.org/groups/802/20/Contribs.
11. H. Song, "Low density parity check (LDPC) code concatenated with generalized partial response (GPR) target for high-capacity magneto-optic(mo) recording channels," Jpn. J. Appl. Phys., pp. 1749-1752, Mar. 2002.
12. B. Vasic, "Low-density parity-check codes and iterative decoding for long-haul optical communication systems," J. Lightw. Technol., vol. 21, no. 2, pp. 438-446, Feb. 2003.
13. C. Lan, "Scalable image and video transmission using irregular repeat-accumulate codes with fast algorithm for optimal unequal error protection," IEEE Trans. Commun., vol. 52, no. 7, pp. 1092-1101, Jul. 2004.
14. R. M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. Inf. Theory, vol. IT-27, pp. 533-547, Sep. 1981.
15. T. Richardson, M. Shokrollahi, and R. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.
16. J. Zhang and M. P. C. Fossorier, "Shuffled iterative decoding," IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005.
17. F. Guilloud, "Generic architecture for LDPC decoding," Ph.D. dissertation, Ecole Nationale Superieure des Télécommunications (ENST), Paris, France, Jul. 2004.
18. E. Yeo, "High throughput low-density parity-check decoder architectures," in Proc. IEEE Global Telecommunications Conf. (IEEE GLOBECOM), San Antonio, TX, Nov. 2001, pp. 3019-3024.
19. R. M. Tanner, "LDPC block and convolutional codes based on circulant matrices," IEEE Trans. Inf. Theory, vol. 50, no. 12, pp. 2966-2984, Dec. 2004.
20. M. Yang, "Design of efficiently encodable moderate-length high-rate irregular LDPC codes," IEEE Trans. Commun., vol. 52, no. 4, pp. 564-571, Apr. 2004.
21. S. t. Brink, "Convergence behavior of iteratively decoded parallel concatenated codes," IEEE Trans. Commun., vol. 49, no. 10, pp. 1727-1737, Oct. 2001.
22. A. Roumy, S. Guemghar, G. Caire, and S. Verdu, "Design methods for irregular repeat-accumulate codes," IEEE Trans. Inf. Theory, vol. 50, no. 8, pp. 1711-1727, Aug. 2004.
23. J. Pearl, Probabilistic Reasoning in Intelligent Systems: Networks of Plausible Inference. San Mateo, CA: Morgan Kaufmann, 1988.
24. R. J. Mcliece, D. J. C. Mackay, and J.-F. Cheng, "Turbo decoding as an instance of Pearl's "belief propagation" algorithm," IEEE J. Sel. Areas Commun., vol. 16, pp. 140-152, Feb. 1998.
25. F. R. Kschischang and B. J. Frey, "Iterative decoding of compound codes by probability propagation in graphical models," IEEE J. Sel. Areas Commun., vol. 16, pp. 219-230, Feb. 1998.
26. L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inf. Theory, vol. 20, pp. 284-287, Mar. 1974.
27. M. M. Mansour and N. R. Shanbhag, "High-throughput LDPC decoders," IEEE Trans. VLSI Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003.
28. X. Y. Hu, "Efficient implementations of the sum-product algorithm for decoding LDPC codes," in Proc. IEEE Global Telecommunications Conf. (IEEE GLOBECOM), San Antonio, TX, Nov. 2001, pp. 1036-1036E.
29. W. J. Gross, V. C. Gaudet, and P. G. Gulak, "Difference metric soft-output detection: Architecture and implementation," IEEE Trans. Circuits Syst. Part II, Analog Digit. Signal Process., vol. 48, no. 10, pp. 904-911, Oct. 2001.
30. M. Tüchler and J. Hagenauer, "EXIT charts of irregular codes," presented at the Conf. Info. Sciences Systems, Princeton University, Princeton, NJ, Mar. 2002.
31. M. M. Mansour, "Design of repeat-accumulate codes from graphs with large girth," presented at the 39th Annual Conf. Information Sciences Systems (CISS), The Johns Hopkins Univ., Baltimore, MD,Mar. 2005.
32. A. Blanksby and C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
33. M. M. Mansour and N. R. Shanbhag, "Architecture-aware low-density parity-check codes," in Proc. IEEE Int. Symp. Circuits Systems (ISCAS), Bangkok, Thailand, May 2003, vol. 2, pp. 57-60.
34. R. M. Tanner, D. Sridhara, and T. Fuja, "A class of group-structured LDPC codes," in Proc. Int. Symp. Communication Theory Applications, Ambleside, U.K., 2001, pp. 1-5.
35. D. Hocevar, "LDPC code construction with flexible hardware," in Proc. IEEE Int. Conf. Communications (ICC), Anchorage, AK, May 2003, pp. 2708-2712.
36. R. M. Tanner, "On quasi-cyclic repeat-accumulate codes," presented at the Proc. 37th Allerton Conf. Communication, Control, Computing, Monticello, IL, Sep. 1999.
37. A. Lubotzky, R. Phillips, and P. Sarnak, "Ramanujan graphs," Combinatorica, vol. 8, no. 3, pp. 261-277, 1988.
38. G. A. Margulis, "Explicit constructions of graphs without short cycles and low density codes," Combinatorica, vol. 2, no. 1, pp. 71-78, 1982.
39. J. Rosenthal and P. O. Vontobel, "Constructions of LDPC codes using Ramanujan graphs and ideas from Margulis," in Proc. 38th Allerton Conf. Communication, Control, Computing, 2000, pp. 248-257.
40. M. M. Mansour and N. R. Shanbhag, "Construction of LDPC codes from Ramanujan graphs," presented at the Ann. Conf. Information Sciences Systems (CISS), Princeton Univ., Princeton, NJ, Mar. 2002.
41. M. M. Mansour and N. R. Shanbhag, "On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures," Proc. 37th Ann. Conf. Information Sciences Systems (CISS) The Johns Hopkins Univ.. Baltimore, MD, Mar. 2003, pp. 215-220.
42. M. M. Mansour and N. R. Shanbhag, "Low-power VLSI decoder architectures for LDPC codes," in Proc. Int. Symp. Low Power Electronics Design (ISLPED). Monterey, CA:, Aug. 2002, pp. 284-289.
43. V. E. Benes, "Optimal rearrangeable multistage connecting networks," Bell Syst. Tech. J., vol. 43, pp. 1641-1656, 1964.
44. G. Royle, CubicHCages [Online]. Available: [Online]. Available: http://www.cs.uwa.edu.au/gordon/cages/index.html.
45. H. Jin, "Analysis and design of turbo-like codes," Ph.D. dissertation, Elect. Eng. Dept., California Inst. Technology, Pasadena, CA, 2001.