Difference metric soft-output detection: Architecture and implementation

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 10, 2001, Pages 904-911

  Gross, Warren J ^a,b   Gaudet, Vincent C ^a,b   Gulak, P Glenn ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

CMOS digital integrated circuits; Digital communication; MAP estimation; Partial response signaling; Very large scale integration

Indexed keywords

CLASS-IV PARTIAL RESPONSE SIGNALING; CMOS DIGITAL INTEGRATED CIRCUITS; FORWARD-BACKWARD DETECTION ALGORITHM; MAXIMUM A POSTERIORI ESTIMATION; SOFT-OUTPUT FORWARD BACKWARD DETECTION; SOFT-OUTPUT VITERBI ALGORITHM; VITERBI ALGORITHM;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DECODING; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MAGNETIC RECORDING;

VLSI CIRCUITS;

EID: 0035493691     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.974777     Document Type: Article

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