Closed-loop nonlinear modeling of wideband ΣΔ fractional-N frequency synthesizers

IEEE Transactions on Microwave Theory and Techniques

Volumn 54, Issue 10, 2006, Pages 3654-3663

  Hedayati, Hiva ^a,b   Bakkaloglu, Bertan ^a,b   Khalil, Waleed ^a,c  

^a IEEE   (United States)

^b Arizona State University   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Fractional N frequency synthesizers; Phase noise; Phase locked loops (PLLs); Quantization noise; Sigma delta modulation; Spurs

Indexed keywords

FRACTIONAL-N FREQUENCY SYNTHESIZERS; PHASE NOISE; QUANTIZATION NOISE; SPURS;

BANDWIDTH; CLOSED LOOP CONTROL SYSTEMS; DELTA SIGMA MODULATION; PARAMETER ESTIMATION; PHASE LOCKED LOOPS; VOLTAGE CONTROL;

FREQUENCY SYNTHESIZERS;

EID: 33749835836     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2006.882872     Document Type: Article

References (25)

1. I. Galton, "Delta-sigma data conversion in wireless transceivers," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 302-315, Jan. 2002.
2. M. S. J. Steyaert, B. De Muer, P. Leroux, M. Borremans, and K. Mertens, "Low-voltage low-power CMOS-RF transceiver design," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 281-287, Jan. 2002.
3. S. E. Meninger and M. H. Perrott, "A fractionnl-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 839-849, Nov. 2003.
4. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, no. 9, pp. 53-559, May 1993.
5. W. Rhee, B.-S. Song, and A. Ali, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-bit third-order SA modulator," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1453-1460, Aug. 2000.
6. B. De Muer and M. S. J. Steyaert, "A CMOS monolithic SA-controlled fractional-N frequency synthesizer for DCS-1800," IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 835-844, Jul. 2002.
7. B. Bisla, R. Eline, and L. M. Franca-Neto, "RF system and circuit challenges for WiMAXs," Intel Technol. J., vol. 08, no. 03, pp. 189-200, Aug. 2004.
8. T. Pollet, M. Van Blade, and M. Moeneclaey, "BER sensitivity of OFDM systems to carrier frequency offset and Wiener phase noise," IEEE Trans. Comm., vol. 43, no. 2, pp. 191-193, Feb. 1995.
9. T. A. D. Riley, N. M. Filiol, D. Qinghong, and J. Kostamovaara, "Techniques for in-band phase noise reduction in EA synthesizers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 794-803, Nov. 2003.
10. S. Pamarti, L. Jansson, and I. Galton, "A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, Jun. 2003.
11. S. E. Meninger and M. H. Perrott, "Bandwidth extension of low noise fractional-N synthesizers," in IEEE Radio Freq. Integr. Circuits Conf., Jun. 2005, pp. 211-214.
12. Y. Dufour, "Method and apparatus for performing fractional division charge compensation in a frequency synthesizer," U.S. Patent 6130561, Oct. 10, 2000.
13. M. H. Perrott, M. D. Trott, and C. G. Sodini, "A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002.
14. B. De Muer and M. S. J. Steyaert, "On the analysis of ΣΔ fractional-N frequency synthesizers for high-spectral purity," IEEE Trans. Circuits Syst. II, Analog Dig. Signal Process., vol. 50, no. 11, pp. 793-784, Nov. 2003.
15. H. Arora, N. Klemmer, J. C. Morizio, and P. D. Wolf, "Enhanced phase noise modeling of fractional-N frequency synthesizers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 379-395, Feb. 2005.
16. C. Y. Lau and M. H. Perrott, "Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm," in IEEE Proc. Design Automat. Conf., Jun. 2003, pp. 526-532.
17. M. Xiaojian, Y. Hauzhang, and W. Hui, "Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer," in IEEE Proc. Int. Behavioral Modeling and Simulation Conf., Oct. 2004, pp. 25-30.
18. M. Kozak and I. Kale, "Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesizers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, pp. 1148-1162, Jun. 2004.
19. R. M. Gray, "Quantization noise spectra," IEEE Trans. Inform. Theory, vol. 36, no. 11, pp. 1220-1244, Nov. 1990.
20. V. Friedman, "The structure of limit cycles in sigma - delta modulation," IEEE Trans. Comm., vol. 36, no. 8, pp. 972-979, Aug. 1988.
21. B. Razavi, RF Microelectronics. Piscataway, NJ: IEEE Press, 1997.
22. C. S. Vaucher, Architectures for RF Frequency Synthesizers. Boston, MA: Kluwer, 2002.
23. E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, "A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446-1454, Sep. 2004.
24. K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez, and S. H. K. Embabi, "A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, Jun. 2003.
25. F. Gardner, "Charge-pump phase lock loops," IEEE Trans. Comm., vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.