A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced Quantization-Induced Phase Noise

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 11, 2003, Pages 839-849

  Meninger, Scott E ^a   Perrott, Michael H ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Frequency synthesizers; Phase noise; Phased locked loops (PLLs); Sigma delta modulation

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; DELTA SIGMA MODULATION; DIGITAL TO ANALOG CONVERSION; MODULATORS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE;

PHASE FREQUENCY DETECTORS (PFD); PHASE NOISE;

FREQUENCY SYNTHESIZERS;

EID: 0344861830     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.819114     Document Type: Article

References (17)

1. U. L. Rohde, Digital PLL Frequency Synthesizers, Theory and Design. Englewood Cliffs, NJ: Prentice-Hall, 1983.
2. T. A. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-Sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
3. B. Miller and R. J. Conley, "A multiple modulator fractional divider," IEEE Trans. Instrum. Meas., vol. 40, pp. 578-583, June 1991.
4. I. Galton, "Delta-Sigma data conversion in wireless transceivers," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 302-315, Jan. 2002.
5. M. Perrott, T. Tewksbuty, and C. Sodini, "A 27 mW fractional-N synthesizer using digital compensation for 2.5 Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 44, pp. 2048-2059, Dec. 1997.
6. B. De Muer and M. Steyaert, "A CMOS monolithic ΣΔ-controlled fractional-N frequency synthesizer for DCS-1800, " IEEE J. Solid-State Circuits, vol. 37, pp. 835-844, July 2002.
7. W. Rhee, B. Song, and A. Ali, "A 1.1 GHz CMOS fractional-N frequency synthesizer with 3-b third-order ΣΔ modulator," IEEE J. Solid-State Circuits, vol. 35, pp. 1453-1460, Oct. 2000.
8. C. Park, O. Kim, and B. Kim, "A 1.8 GHz self-calibrated phase-locked loop with precise I/Q matching," IEEE J. Solid-State Circuits, vol. 36, pp. 777-783, May 2001.
9. K. Lee et al., "A single chip 2.4 GH direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique," IEEE J. Solid-State Circuits, vol. 36, pp. 800-809, May 2001.
10. W. Rhee and A. Ali, "An on-chip compensation technique in fractional-N frequency synthesis," in Proc. IEEE ISCAS, vol. 3, July 1999, pp. 363-366.
11. T. A. Riley and J. Kostamovaara, "A hybrid ΣΔ fractional-N frequency synthesizer," IEEE Trans. Circuits Syst. II, vol. 50, pp. 176-180, Apr. 2003.
12. S. Pamarti and I. Galton, "Phase noise cancellation design tradeoffs in delta-sigma fractional-N PLLs," IEEE Trans. Circuits Syst. II, pp. 829-838, Nov. 2003.
13. Y. Dufour, "Method and Apparatus for Performing Fractional Division Charge Compensation in a Frequency Synthesizer," U.S. Patent 6 130 561, 2000.
14. S. Norswothy, R. Schreier, and G. Ternes, Delta-Sigma Data Converters: Theory, Design, and Simulation. Piscataway, NJ: IEEE Press, 1997.
15. C. Y. Lau and M. H. Perrott, "Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm," in Proc. IEEE Design Automation Conf., June 2003, pp. 526-531.
16. M. Perrott, "Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits," in Proc. IEEE 39th Annu. Design Automation Conf., 2002, pp. 498-503.
17. M. Perrott, M. Trott, and C. Sodini, "A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002.