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Volumn , Issue , 2005, Pages 211-214

Bandwidth extension of low noise fractional-N synthesizers

Author keywords

Fractional N; Frequency Synthesis; Jitter; Phase noise; Sigma delta

Indexed keywords

BANDWIDTH; DELTA SIGMA MODULATION; JITTER; NOISE ABATEMENT; SPURIOUS SIGNAL NOISE;

EID: 27644443116     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (9)
  • 1
    • 0027590694 scopus 로고
    • Delta - Sigma modulation in fractional- N frequency synthesis
    • May
    • T.A. Riley, M. A. Copeland, and T.A. Kwasniewski, "Delta - Sigma Modulation in Fractional- N Frequency Synthesis," IEEE JSSC, vol. 28, pp. 553-559, May 1993
    • (1993) IEEE JSSC , vol.28 , pp. 553-559
    • Riley, T.A.1    Copeland, M.A.2    Kwasniewski, T.A.3
  • 2
    • 0344861830 scopus 로고    scopus 로고
    • A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise
    • Nov.
    • S.E. Meninger and M.H. Perrott, "A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," IEEE Trans. Circuits Syst. II, vol. 50, pp. 839-849, Nov. 2003.
    • (2003) IEEE Trans. Circuits Syst. II , vol.50 , pp. 839-849
    • Meninger, S.E.1    Perrott, M.H.2
  • 3
    • 0036685487 scopus 로고    scopus 로고
    • A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis
    • Aug.
    • M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002.
    • (2002) IEEE J. Solid-state Circuits , vol.37 , pp. 1028-1038
    • Perrott, M.H.1    Trott, M.D.2    Sodini, C.G.3
  • 5
    • 0742268982 scopus 로고    scopus 로고
    • A wideband 2.4GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation
    • Jan.
    • S.Parmarti, L. Jansson, and I. Galton, "A Wideband 2.4GHz Delta-Sigma Fractional-N PLL With 1-Mb/s In-Loop Modulation," IEEE J. Solid-State Circuits, vol. 39, pp. 49-62, Jan. 2004.
    • (2004) IEEE J. Solid-state Circuits , vol.39 , pp. 49-62
    • Parmarti, S.1    Jansson, L.2    Galton, I.3
  • 6
    • 4444377645 scopus 로고    scopus 로고
    • A 700kHz bandwidth SD fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications
    • Sept.
    • E. Temporitit, et. al, "A 700kHz Bandwidth SD Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMA Applications," IEEE J. Solid-State Circuits, vol. 39, pp. 1446-1454, Sept. 2004.
    • (2004) IEEE J. Solid-state Circuits , vol.39 , pp. 1446-1454
    • Temporitit, E.1
  • 9
    • 24944538548 scopus 로고    scopus 로고
    • All-digital PLL and SM/EDGE transmitter in 90nm CMOS
    • Feb.
    • R. Bogdan, et. al., "All-Digital PLL and SM/EDGE Transmitter in 90nm CMOS," 2005 IEEE ISSCC Digest of Technical Papers, pp. 316-317, Feb. 2005
    • (2005) 2005 IEEE ISSCC Digest of Technical Papers , pp. 316-317
    • Bogdan, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.