An on-chip dynamically recalibrated delay line for embedded self-timed systems

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2000, Pages 45-51

  Taylor, George ^a   Moore, Simon ^a   Wilcox, Steev ^a   Laboratory, Peter Robinson ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY LINE; FPGA TECHNOLOGY; LOW FREQUENCY; LOW POWER; OFF-CHIP INTERFACES; OFF-CHIP MEMORIES; ON CHIPS; RECALIBRATIONS; SELF-TIMED; SELF-TIMED SYSTEMS; STANDARD CELL; TWO DELAYS;

DESIGN; ELECTRIC BATTERIES; ELECTRIC DELAY LINES; EMBEDDED SYSTEMS; TIME SHARING SYSTEMS; WAVES;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 84455182953     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2000.836786     Document Type: Conference Paper

References (10)

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