Scalable hardware priority queue architectures for high-speed packet switches

IEEE Transactions on Computers

Volumn 49, Issue 11, 2000, Pages 1215-1227

  Moon, Sung Whan ^a,c   Rexford, Jennifer ^b,c   Shin, Kang G ^a,c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b AT AND T LABS RESEARCH   (United States)

^c IEEE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; PACKET SWITCHING; PERFORMANCE; PROGRAM COMPILERS; QUALITY OF SERVICE; QUEUEING NETWORKS; REAL TIME SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING; TELECOMMUNICATION LINKS; VLSI CIRCUITS;

EPOCH SILICON COMPILER; LINK SCHEDULING; PRIORITY QUEUE ARCHITECTURES; VERILOG HARDWARE DESCRIPTION LANGUAGE;

COMPUTER ARCHITECTURE;

EID: 0034316208     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.895938     Document Type: Article

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