Automating production of run-time reconfigurable designs

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 1-10

  Shirazi, N ^a   Luk, W ^a   Cheung, P Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; IMAGE PROCESSING; PATTERN MATCHING;

BIPARTITE GRAPHS; CIRCUIT CONFIGURATIONS; MATCHING ALGORITHM; RECONFIGURABLE; RECONFIGURATION TIME; RUN-TIME RECONFIGURABLE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33747870341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707892     Document Type: Conference Paper

References (8)

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2. J.E. Hopcroft and R.M. Karp, "An n5=2 Algorithm For Maximum Matchings in Bipartite Graphs", in SIAM Journal of Computing, Vol. 2, No. 4, December 1973, pp. 225-231.
3. W. Luk, S. Guo, N. Shirazi and N. Zhuang, "A Framework for Developing Parametrised FPGA Libraries", in Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, R. Hartenstein and M. Glesner (eds.), LNCS 1142, Springer, 1996, pages 24-33.
4. W. Luk, N. Shirazi and P.Y.K. Cheung, "Modelling and Optimising Run-Time Reconfigurable Systems", in Proc. FCCM96, K.L. Pocek and J. Arnold (eds.), IEEE Computer Society Press, 1996, pp. 167-176.
5. W. Luk, N. Shirazi, S.R. Guo and P.Y.K. Cheung, "Pipeline Morphing and Virtual Pipelines", in Field Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (eds.), LNCS 1304, Springer, 1997, pp. 111-120.
6. W. Luk, N. Shirazi and P.Y.K. Cheung, "Compilation Tools for Run-Time Reconfigurable Designs", in Proc. FCCM97, K.L. Pocek and J. Arnold (eds.), IEEE Computer Society Press, 1997, pp. 56-65.
7. D.B. West, Introduction to Graph Theory, Prentice Hall, 1996.
8. M.J. Wirthlin and B.L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", in FPGA'97, ACM Press, 1997, pp. 86-92.